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296 Commits
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296 Commits (d40f39a0918f2d3ca67d70f10aab06ad8743400d)

Author SHA1 Message Date
liangkangnan 1ccdeb1b81 example: coremark: fix build error 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-21 22:34:15 +08:00
liangkangnan b0c4d1fa4d rtl:timer: update interrupt assert 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-12 22:33:15 +08:00
liangkangnan 6f5fe893cb README: update 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-11 16:09:59 +08:00
liangkangnan 506abe158f README: update 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-07 23:15:45 +08:00
liangkangnan 4049559948 fpga: README: update 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-07 23:09:48 +08:00
liangkangnan 43c3510fc2 README.md: update 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-05 23:03:54 +08:00
liangkangnan 6642662e71 fpga: add burn mcs file 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-04 22:58:25 +08:00
liangkangnan 96b2eca546 tb: set uart debug disable 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-04 17:31:58 +08:00
liangkangnan 15f10fbf35 sim: add uart_debug.v 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-04 17:21:50 +08:00
liangkangnan f7b3dc8327 fpga: README: add uart download 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-04 16:27:53 +08:00
liangkangnan ab185de7f5 tools: add uart download script 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-04 14:36:02 +08:00
liangkangnan 1c51a4e515 README: add uart download 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-04 14:34:46 +08:00
liangkangnan 8c751095fd fpga: constrs: add uart_debug_en pin 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-04 14:33:33 +08:00
liangkangnan a73b0ea36b rtl: add uart_debug module 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-04 14:32:31 +08:00
Blue Liang 4813893a34 sim: compliance_test: compare files line by line 
Signed-off-by: Blue Liang <liangkangnan@163.com>
 2020-06-28 20:26:12 +08:00
liangkangnan a945cd1512 pic: update arch.jpg 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-27 10:11:46 +08:00
liangkangnan 890a6266f3 tests: example: add uart rx 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-26 22:46:03 +08:00
liangkangnan 1486b5aca8 sim: change uart_tx.v to uart.v 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-26 22:44:14 +08:00
liangkangnan 317061682d fpga: constrs: add uart rx pin 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-26 22:41:48 +08:00
liangkangnan 4c6c044afb rtl: add uart rx function 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-26 22:40:44 +08:00
liangkangnan 405b3fb0c3 tb: add README.md 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-21 21:32:10 +08:00
liangkangnan 193794cf5c README: update 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-21 21:28:07 +08:00
liangkangnan f2010755bb fpga: constrs: add spi flash config 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-14 22:13:44 +08:00
liangkangnan 2c8762a102 example: freertos: init gpio mode 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-14 22:06:25 +08:00
liangkangnan f10a4ac49b example: timer_int: init gpio mode 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-14 22:04:38 +08:00
liangkangnan 6b01facc48 example: gpio: add input usage 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-14 10:45:55 +08:00
liangkangnan 5c70814fc6 fpga: constrs: add one more gpio 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-14 10:41:52 +08:00
liangkangnan 2619f26eae gpio: add input function 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-14 10:40:25 +08:00
liangkangnan e28381dbcf add support for ebreak inst 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-13 14:56:44 +08:00
liangkangnan 5f64a5f8ae fpga: update README.md 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-07 21:55:28 +08:00
liangkangnan 764ecc7199 delete README.en.md 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-07 13:25:14 +08:00
liangkangnan 5b888bd483 rtl: core: fix data related for csr regs 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-05 22:22:49 +08:00
liangkangnan 0256674146 compliance test: add rv32Zicsr and rv32Zifencei build 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-05 22:19:49 +08:00
liangkangnan c3e607ec55 sim: compliance_test: fix can not find ref file 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-05 22:16:36 +08:00
liangkangnan 69484de8b2 openocd: tinyriscv.cfg: add halt cmd 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-31 21:05:18 +08:00
liangkangnan de9a978417 fix: must exit openocd after download temporary 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-31 14:41:39 +08:00
liangkangnan eec414aa96 use = instead of <= 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-31 14:38:57 +08:00
liangkangnan 1dea4a0a5e fpga: README: exit openocd after download 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-31 12:14:29 +08:00
liangkangnan 09d45f9ea9 rename FPGA to fpga 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-31 12:05:28 +08:00
liangkangnan dfbb1ed6c1 sim: compliance_test: add README.md 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-27 23:47:55 +08:00
liangkangnan 8cb261b079 sim: add README.md 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-27 23:43:35 +08:00
liangkangnan 0a7d7616ab add new inst test 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-27 23:24:33 +08:00
liangkangnan 38c2245218 sim: remove tb file to tb dir 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-27 23:17:05 +08:00
liangkangnan f775abf1d7 sim: add compliance test script 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-27 23:08:43 +08:00
liangkangnan 362d188458 use tb file in tb dir 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-27 23:07:14 +08:00
liangkangnan 897a346788 remove .elf 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-27 23:05:39 +08:00
liangkangnan 7d877c3348 tests: add riscv-compliance 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-27 23:04:07 +08:00
liangkangnan eb65d0badc FPGA: update simulation settings 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-24 13:37:45 +08:00
liangkangnan ea0734b280 FPGA: add vivado sim 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-21 22:04:23 +08:00
liangkangnan edee04cfe2 sim: fix vivado error 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-21 21:53:08 +08:00