liangkangnan
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ad3dbd1a51
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rtl:core: add bootrom and xip module address
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2023-04-01 15:32:56 +08:00 |
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liangkangnan
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b3cfa2dfa6
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rtl: do not need request all the access period
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2023-04-01 14:12:59 +08:00 |
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liangkangnan
|
d6a14415c9
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rtl: optimized for instr fetch and mem access
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2023-03-28 10:19:07 +08:00 |
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liangkangnan
|
3120110be3
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rtl:core: ifu support for boot from flash
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-11-25 09:00:09 +08:00 |
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liangkangnan
|
15928977e1
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rtl:perips: add flash_ctrl module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-11-02 10:54:37 +08:00 |
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liangkangnan
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22a038cc09
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rtl🔝 add more perips
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-09-10 09:57:39 +08:00 |
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liangkangnan
|
57690b00bd
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rtl:perips: add spi master
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-09-06 10:01:56 +08:00 |
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liangkangnan
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ae3ff5a211
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rtl🚌 use gnt and rvalid signal
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-09-01 09:54:32 +08:00 |
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liangkangnan
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2afcba47ea
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rtl:perips: add i2c master
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-19 09:43:12 +08:00 |
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liangkangnan
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64041b4d2b
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rtl: perips: rewrite timer module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-10 09:47:37 +08:00 |
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liangkangnan
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58f180a92f
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rtl: perips: rewrite uart module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-07 14:28:46 +08:00 |
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liangkangnan
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cba47c1f64
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use none-vector interrupt mode
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-26 09:54:38 +08:00 |
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liangkangnan
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3227fb1ffd
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rtl:perips: add rvic
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-22 09:36:04 +08:00 |
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liangkangnan
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18de7f2e00
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test: use csr_sstatus for test result
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-10 14:49:36 +08:00 |
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liangkangnan
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fd2c981317
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-09 15:18:09 +08:00 |
|
liangkangnan
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53e4263706
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rtl: ifu optimization
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-03 15:09:13 +08:00 |
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liangkangnan
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34218536c1
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-01 09:46:56 +08:00 |
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liangkangnan
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3269041c0b
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rtl: add config for branch predictor
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-28 11:31:04 +08:00 |
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liangkangnan
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5f56e8d0fb
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-18 20:04:46 +08:00 |
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liangkangnan
|
7196d33074
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rtl: add static branch predict unit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-11 09:44:26 +08:00 |
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liangkangnan
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f9f78976fb
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rtl: core: optimize mem access
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-05 20:00:15 +08:00 |
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liangkangnan
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fb461a6176
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-25 11:45:53 +08:00 |
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liangkangnan
|
c6163aaff1
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-25 09:41:00 +08:00 |
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liangkangnan
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01c3159a83
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use larger ram
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-21 09:43:34 +08:00 |
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liangkangnan
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5efa66ee64
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debug: fix breakpoint
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-19 19:09:17 +08:00 |
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liangkangnan
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f08fd1b17e
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debug: fix step
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-19 15:35:11 +08:00 |
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liangkangnan
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136dc45a09
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change core clock to 25MHZ
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-17 16:40:25 +08:00 |
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liangkangnan
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536d28ede3
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-17 10:22:04 +08:00 |
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liangkangnan
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6e466fbbf7
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add perips
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-14 21:00:57 +08:00 |
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liangkangnan
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5811bdde13
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debug: add hw breakpoint support
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-14 14:37:47 +08:00 |
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liangkangnan
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b02b38bddc
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-11 16:21:58 +08:00 |
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liangkangnan
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36147d9391
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-11 10:35:36 +08:00 |
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liangkangnan
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4a4c08bc69
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-04 21:11:43 +08:00 |
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liangkangnan
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10d8d35a13
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rtl: fix combilation loop
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-02 14:51:12 +08:00 |
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liangkangnan
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738fba1d6f
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-30 18:27:30 +08:00 |
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liangkangnan
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f9412fca3c
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-29 19:27:25 +08:00 |
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liangkangnan
|
ec65381ba9
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-25 17:14:09 +08:00 |
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liangkangnan
|
462cc4c786
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-13 19:49:09 +08:00 |
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liangkangnan
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9ac1b31965
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rtl: add reset module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-13 14:12:47 +08:00 |
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liangkangnan
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7803e89d68
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-13 11:10:06 +08:00 |
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liangkangnan
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e53f681063
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rtl: optimize csr regs
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-13 09:25:29 +08:00 |
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liangkangnan
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bd2d372c66
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-12 19:18:35 +08:00 |
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liangkangnan
|
ad775ef316
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-09 20:27:33 +08:00 |
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liangkangnan
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f1f09584ee
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optimize ifu and lsu
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-09 20:22:34 +08:00 |
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liangkangnan
|
e3667e0ddd
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-01 11:29:00 +08:00 |
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liangkangnan
|
9943d02600
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-03-31 18:00:19 +08:00 |
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liangkangnan
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c070f0b49d
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-03-31 15:25:22 +08:00 |
Blue Liang
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8214134b89
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tmp commit, unstable
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-03-29 15:14:50 +08:00 |
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liangkangnan
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fdc776ab5e
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rtl: debug: support reset cmd
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-12-06 20:06:12 +08:00 |
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liangkangnan
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f03f42fc9b
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rtl: add reset ctrl module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-11-18 22:15:08 +08:00 |