liangkangnan
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e23ad11e7e
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rtl: fix sync interrupt return address
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-07-25 22:15:03 +08:00 |
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liangkangnan
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b39062a4ea
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rtl: fix interrupt return address
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-07-25 16:23:45 +08:00 |
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liangkangnan
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a73b0ea36b
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rtl: add uart_debug module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-07-04 14:32:31 +08:00 |
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liangkangnan
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e28381dbcf
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add support for ebreak inst
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-06-13 14:56:44 +08:00 |
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liangkangnan
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5b888bd483
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rtl: core: fix data related for csr regs
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-06-05 22:22:49 +08:00 |
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liangkangnan
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eec414aa96
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use = instead of <=
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-05-31 14:38:57 +08:00 |
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liangkangnan
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260246f488
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fix nop inst
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-05-07 22:40:31 +08:00 |
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liangkangnan
|
07b33baf94
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perips: add spi master
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-05-05 18:31:08 +08:00 |
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liangkangnan
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837af2c977
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use = instead of <= in combination logic
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-05-02 11:58:44 +08:00 |
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liangkangnan
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aead35700c
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add signal
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-25 17:15:46 +08:00 |
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liangkangnan
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02d19b9e6f
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add mie and mstatus reg
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-25 17:13:12 +08:00 |
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liangkangnan
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4a530ab894
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add ECALL inst
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-25 17:11:53 +08:00 |
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liangkangnan
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43aca8195c
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add clint hold input signal
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-25 17:08:46 +08:00 |
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liangkangnan
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6cf86e0286
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stop div when interrupt assert
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-25 17:04:44 +08:00 |
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liangkangnan
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09513f8f2c
|
support preemption
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-25 17:03:13 +08:00 |
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liangkangnan
|
dcac95dfab
|
add code comments
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-18 20:14:37 +08:00 |
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liangkangnan
|
ce225394df
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fix reg1 reg2 bits width
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-18 11:35:43 +08:00 |
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liangkangnan
|
b29781a8de
|
optimize div
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-18 11:23:46 +08:00 |
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liangkangnan
|
2638240d0b
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add mepc reg
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-18 11:22:20 +08:00 |
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liangkangnan
|
96f8d6e5a0
|
optimized: use statemachine
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-18 11:21:09 +08:00 |
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liangkangnan
|
0e188d4934
|
reorganize example and optimize interrupt
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-11 19:03:49 +08:00 |
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liangkangnan
|
a68f31b604
|
perips: add uart_tx and gpio
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-05 22:27:00 +08:00 |
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liangkangnan
|
6660f18b3d
|
support CSR inst
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-05 22:22:34 +08:00 |
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liangkangnan
|
ecb9fca8c1
|
update
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-03-29 23:19:14 +08:00 |
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liangkangnan
|
8b51737477
|
add interrupt support and example
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-03-08 15:09:30 +08:00 |
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liangkangnan
|
8208cbc100
|
support JTAG
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-03-01 14:55:36 +08:00 |