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Commit Graph

  • 6143d9ee6a rtl:gpio: remove gpio.h liangkangnan 2021-08-17 10:20:30 +0800
  • 12467d1554 sdk:bsp: adapte to new rvic liangkangnan 2021-08-14 14:05:08 +0800
  • d4b670217a rtl:perips: rewrite rvic liangkangnan 2021-08-14 14:03:47 +0800
  • 477d9efc34 sdk:examples: adapte to new perips liangkangnan 2021-08-13 10:07:13 +0800
  • fdd953c0f0 sdk:bsp: update gpio liangkangnan 2021-08-13 09:35:56 +0800
  • 5fa659a084 rtl:perips: rewrite gpio liangkangnan 2021-08-13 09:33:15 +0800
  • 9387f56a33 sdk:examples: add uart_int liangkangnan 2021-08-13 09:31:19 +0800
  • aaa5684cc9 sdk:bsp: remove machine_timer liangkangnan 2021-08-11 14:47:35 +0800
  • 0437ff99da sdk: examples: remove machine_timer liangkangnan 2021-08-10 11:30:08 +0800
  • 79f83c1ad4 tmp commit liangkangnan 2021-08-10 11:26:46 +0800
  • ad5adcb843 tmp commit liangkangnan 2021-08-10 11:09:53 +0800
  • c4fe45ffaf sdk: examples: add timer liangkangnan 2021-08-10 09:54:20 +0800
  • 64041b4d2b rtl: perips: rewrite timer module liangkangnan 2021-08-10 09:47:37 +0800
  • f6c8a046c7 tools:regtool: add README.md liangkangnan 2021-08-07 15:26:12 +0800
  • c178a8fbb2 tools: add regtool liangkangnan 2021-08-07 15:07:44 +0800
  • 72b982d133 sdk:lib: rewrite uart liangkangnan 2021-08-07 14:30:29 +0800
  • 58f180a92f rtl: perips: rewrite uart module liangkangnan 2021-08-07 14:28:46 +0800
  • cba47c1f64 use none-vector interrupt mode liangkangnan 2021-07-26 09:54:38 +0800
  • 9e7653a96a sdk:bsp: adapt to rvic liangkangnan 2021-07-22 09:40:26 +0800
  • 3227fb1ffd rtl:perips: add rvic liangkangnan 2021-07-22 09:36:04 +0800
  • e9044a7efe tests:random_instruction: add .gitignore liangkangnan 2021-07-12 19:46:00 +0800
  • 5ebb41c477 tests/random_instruction: add README.md liangkangnan 2021-07-12 19:29:40 +0800
  • 8f3aa6bb2c tests: add random instruction liangkangnan 2021-07-12 18:22:02 +0800
  • ac245a5d6c tools: add riscv-torture liangkangnan 2021-07-12 18:13:01 +0800
  • 18de7f2e00 test: use csr_sstatus for test result liangkangnan 2021-07-10 14:49:36 +0800
  • fd2c981317 temp commit liangkangnan 2021-07-09 15:18:09 +0800
  • 53e4263706 rtl: ifu optimization liangkangnan 2021-07-03 15:09:13 +0800
  • 34218536c1 temp commit liangkangnan 2021-07-01 09:46:56 +0800
  • 3269041c0b rtl: add config for branch predictor liangkangnan 2021-06-28 11:31:04 +0800
  • 2db9e7dbb9 rtl: add sync_fifo module liangkangnan 2021-06-28 11:09:37 +0800
  • 96d6976c44 temp commit liangkangnan 2021-06-19 16:33:50 +0800
  • 5f56e8d0fb temp commit liangkangnan 2021-06-18 20:04:46 +0800
  • 4e99bd4f33 README: update liangkangnan 2021-06-11 09:49:31 +0800
  • 7196d33074 rtl: add static branch predict unit liangkangnan 2021-06-11 09:44:26 +0800
  • e26dda807e README: update verilator-v0.9 liangkangnan 2021-06-08 19:35:29 +0800
  • f9f78976fb rtl: core: optimize mem access liangkangnan 2021-06-05 20:00:15 +0800
  • 6121a21322 rtl: top: make jtag host highest priority liangkangnan 2021-06-05 19:59:07 +0800
  • 4436e0cc6a tools: update openocd for win liangkangnan 2021-06-05 19:48:41 +0800
  • b7b8572542 tb: add tests type macro liangkangnan 2021-06-05 16:59:26 +0800
  • d9a1f89fd2 tests: riscv-compliance: add support liangkangnan 2021-06-05 16:02:02 +0800
  • 6059c4c3a7 tests: isa: add support liangkangnan 2021-06-05 15:11:33 +0800
  • c847244c5b rtl: perips: fix machine timer liangkangnan 2021-06-03 09:23:50 +0800
  • 646bc96419 openocd: update verilator-v0.8 liangkangnan 2021-05-31 14:07:36 +0800
  • 6d8015727e temp commit liangkangnan 2021-05-31 10:27:01 +0800
  • 247a5b6354 temp commit liangkangnan 2021-05-28 15:10:37 +0800
  • cd9ac0adae debug: change dmi addr bits to 7 liangkangnan 2021-05-28 10:37:50 +0800
  • fb461a6176 temp commit liangkangnan 2021-05-25 11:45:53 +0800
  • c6163aaff1 temp commit liangkangnan 2021-05-25 09:41:00 +0800
  • fd5413791d example: coremark: print tips after uart init liangkangnan 2021-05-22 15:26:24 +0800
  • 1ea770ba7e README: update Blue Liang 2021-05-21 19:55:56 +0800
  • 87849fbd35 README: update liangkangnan 2021-05-21 17:08:46 +0800
  • 5353371516 doc: add obi spec liangkangnan 2021-05-21 17:06:39 +0800
  • bffeebd0bf example:simple: add -g flag liangkangnan 2021-05-21 17:05:56 +0800
  • b98e1c5538 bsp: use self-build gcc liangkangnan 2021-05-21 14:19:50 +0800
  • af63e677d9 example: fix freertos liangkangnan 2021-05-21 09:50:21 +0800
  • 01c3159a83 use larger ram liangkangnan 2021-05-21 09:43:34 +0800
  • a67fba652d add mmcm module for xilinx fpga liangkangnan 2021-05-20 11:05:39 +0800
  • 5efa66ee64 debug: fix breakpoint liangkangnan 2021-05-19 19:09:17 +0800
  • c7a374acb8 temp commit liangkangnan 2021-05-19 16:09:39 +0800
  • f08fd1b17e debug: fix step liangkangnan 2021-05-19 15:35:11 +0800
  • 6cd6532423 example: add uart loopback liangkangnan 2021-05-17 16:56:52 +0800
  • 136dc45a09 change core clock to 25MHZ liangkangnan 2021-05-17 16:40:25 +0800
  • 536d28ede3 temp commit liangkangnan 2021-05-17 10:22:04 +0800
  • b0f4592322 temp commit liangkangnan 2021-05-15 14:52:30 +0800
  • 6e466fbbf7 add perips liangkangnan 2021-05-14 21:00:57 +0800
  • 5811bdde13 debug: add hw breakpoint support liangkangnan 2021-05-14 14:37:47 +0800
  • b02b38bddc temp commit liangkangnan 2021-05-11 16:21:58 +0800
  • 36147d9391 temp commit liangkangnan 2021-05-11 10:35:36 +0800
  • 4a4c08bc69 temp commit liangkangnan 2021-05-04 21:11:43 +0800
  • 10d8d35a13 rtl: fix combilation loop liangkangnan 2021-05-02 14:51:12 +0800
  • 738fba1d6f temp commit liangkangnan 2021-04-30 18:27:30 +0800
  • 53865371ce temp commit liangkangnan 2021-04-30 16:41:24 +0800
  • dfa8bf490e bus: fix bug liangkangnan 2021-04-30 08:59:10 +0800
  • f9412fca3c temp commit liangkangnan 2021-04-29 19:27:25 +0800
  • 77812d60df temp commit liangkangnan 2021-04-26 14:08:26 +0800
  • 4da79b6046 debug: add sba module liangkangnan 2021-04-26 09:48:19 +0800
  • 65a26842c4 temp commit liangkangnan 2021-04-25 19:34:21 +0800
  • ec65381ba9 temp commit liangkangnan 2021-04-25 17:14:09 +0800
  • 462cc4c786 temp commit liangkangnan 2021-04-13 19:49:09 +0800
  • 05e2441d24 temp commit liangkangnan 2021-04-13 16:34:00 +0800
  • 9ac1b31965 rtl: add reset module liangkangnan 2021-04-13 14:12:47 +0800
  • 7803e89d68 temp commit liangkangnan 2021-04-13 11:10:06 +0800
  • e53f681063 rtl: optimize csr regs liangkangnan 2021-04-13 09:25:29 +0800
  • bd2d372c66 temp commit liangkangnan 2021-04-12 19:18:35 +0800
  • 16fa475ba7 rtl:perips: remove vld rdy signals liangkangnan 2021-04-09 20:47:00 +0800
  • ad775ef316 temp commit liangkangnan 2021-04-09 20:27:33 +0800
  • f1f09584ee optimize ifu and lsu liangkangnan 2021-04-09 20:22:34 +0800
  • e3667e0ddd temp commit liangkangnan 2021-04-01 11:29:00 +0800
  • 9943d02600 temp commit liangkangnan 2021-03-31 18:00:19 +0800
  • c070f0b49d temp commit liangkangnan 2021-03-31 15:25:22 +0800
  • 9322b595bc tools: add openocd ex arrt liangkangnan 2021-03-29 19:21:02 +0800
  • e2c07ec19b temp commit Blue Liang 2021-03-29 19:10:02 +0800
  • b4b54d831b temp commit Blue Liang 2021-03-29 18:22:52 +0800
  • f23b545499 tools: BinToMem.py: use unix format liangkangnan 2021-03-29 15:26:19 +0800
  • 8214134b89 tmp commit, unstable Blue Liang 2021-03-29 15:14:50 +0800
  • 18dc85e69e README: update liangkangnan 2021-01-31 21:39:28 +0800
  • 918804fc49 update README liangkangnan 2021-01-24 20:39:45 +0800
  • 5c87fc09ef tb: add jtag testbench bram liangkangnan 2020-12-06 20:07:06 +0800
  • fdc776ab5e rtl: debug: support reset cmd liangkangnan 2020-12-06 20:06:12 +0800
  • f03f42fc9b rtl: add reset ctrl module liangkangnan 2020-11-18 22:15:08 +0800