// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{ name: "uart",
  clocking: [{clock: "clk_i", reset: "rst_ni"}],
  bus_interfaces: [
    { protocol: "tlul", direction: "device" }
  ],
  regwidth: "32",
  registers: [
    { name: "CTRL",
      desc: "UART control register",
      swaccess: "rw",
      hwaccess: "hro",
      hwqe:     "true",
      fields: [
        { bits: "0",
          name: "TX_EN",
          desc: "TX enable"
        }
        { bits: "1",
          name: "RX_EN",
          desc: "RX enable"
        }
        { bits: "2",
          name: "TX_FIFO_EMPTY_INT_EN",
          desc: "Generate interrupt signal when tx fifo empty"
        }
        { bits: "3",
          name: "RX_FIFO_NOT_EMPTY_INT_EN",
          desc: "Generate interrupt signal when rx fifo not empty"
        }
        { bits: "4",
          name: "TX_FIFO_RST",
          desc: "Reset tx fifo",
          swaccess: "r0w1c"
        }
        { bits: "5",
          name: "RX_FIFO_RST",
          desc: "Reset rx fifo",
          swaccess: "r0w1c"
        }
        { bits: "31:16",
          name: "BAUD_DIV",
          desc: "Baud rate divider count",
          resval: "0xD9"
        }
      ]
    }
    { name:     "STATUS"
      desc:     "UART status register"
      swaccess: "ro"
      hwaccess: "hrw"
      hwext:    "true"
      hwre:     "true"
      fields: [
        { bits: "0"
          name: "TXFULL"
          desc: "TX FIFO is full"
        }
        { bits: "1"
          name: "RXFULL"
          desc: "RX FIFO is full"
        }
        { bits: "2"
          name: "TXEMPTY"
          desc: "TX FIFO is empty"
          resval: "1"
        }
        { bits: "3"
          name: "RXEMPTY"
          desc: "RX FIFO is empty"
          resval: "1"
        }
        { bits: "4"
          name: "TXIDLE"
          desc: "TX FIFO is empty and all bits have been transmitted"
          resval: "1"
        }
        { bits: "5"
          name: "RXIDLE"
          desc: "RX is idle"
          resval: "1"
        }
      ]
    }
    { name: "TXDATA",
      desc: "UART TX data register",
      swaccess: "wo",
      hwaccess: "hro",
      hwqe: "true",
      fields: [
        { bits: "7:0" }
      ]
    }
    { name: "RXDATA",
      desc: "UART RX data register",
      swaccess: "ro",
      hwaccess: "hrw",
      hwext: "true",
      hwre: "true",
      fields: [
        { bits: "7:0" }
      ]
    }
  ]
}