liangkangnan 9ac1b31965 rtl: add reset module ... Signed-off-by: liangkangnan <liangkangnan@163.com>		2021-04-13 14:12:47 +08:00
..
clint.sv	temp commit	2021-03-31 18:00:19 +08:00
csr.sv	rtl: optimize csr regs	2021-04-13 09:25:29 +08:00
csr_reg.sv	rtl: optimize csr regs	2021-04-13 09:25:29 +08:00
defines.sv	temp commit	2021-04-13 11:10:06 +08:00
divider.sv	temp commit	2021-03-31 18:00:19 +08:00
exu.sv	optimize ifu and lsu	2021-04-09 20:22:34 +08:00
exu_alu_datapath.sv	temp commit	2021-03-31 18:00:19 +08:00
exu_commit.sv	temp commit	2021-03-31 18:00:19 +08:00
exu_dispatch.sv	temp commit	2021-03-31 18:00:19 +08:00
exu_mem.sv	optimize ifu and lsu	2021-04-09 20:22:34 +08:00
exu_muldiv.sv	temp commit	2021-03-31 18:00:19 +08:00
gpr_reg.sv	temp commit	2021-03-31 18:00:19 +08:00
idu.sv	temp commit	2021-03-31 18:00:19 +08:00
idu_exu.sv	temp commit	2021-04-01 11:29:00 +08:00
ifu.sv	temp commit	2021-04-09 20:27:33 +08:00
ifu_idu.sv	temp commit	2021-04-01 11:29:00 +08:00
pipe_ctrl.sv	temp commit	2021-03-31 18:00:19 +08:00
rst_gen.sv	rtl: add reset module	2021-04-13 14:12:47 +08:00
tinyriscv_core.sv	temp commit	2021-04-13 11:10:06 +08:00
tracer.sv	optimize ifu and lsu	2021-04-09 20:22:34 +08:00