|
clint.v
|
rtl: core: fix sync interrupt
|
2020-08-15 16:05:06 +08:00 |
|
csr_reg.v
|
rtl: core: fix data related for csr regs
|
2020-06-05 22:22:49 +08:00 |
|
ctrl.v
|
use = instead of <= in combination logic
|
2020-05-02 11:58:44 +08:00 |
|
defines.v
|
add support for ebreak inst
|
2020-06-13 14:56:44 +08:00 |
|
div.v
|
stop div when interrupt assert
|
2020-04-25 17:04:44 +08:00 |
|
ex.v
|
rtl: core: optimization
|
2020-08-13 09:01:27 +08:00 |
|
id.v
|
rtl: core: optimization
|
2020-08-13 09:01:27 +08:00 |
|
id_ex.v
|
rtl: core: optimization
|
2020-08-13 09:01:27 +08:00 |
|
if_id.v
|
rtl: fix interrupt return address
|
2020-07-25 16:23:45 +08:00 |
|
pc_reg.v
|
add code comments
|
2020-04-18 20:14:37 +08:00 |
|
regs.v
|
use = instead of <=
|
2020-05-31 14:38:57 +08:00 |
|
rib.v
|
rtl: remove unused signals
|
2020-08-29 22:35:43 +08:00 |
|
tinyriscv.v
|
rtl: core: fix sync interrupt
|
2020-08-15 16:05:06 +08:00 |
0ed81ff1a8