72 lines
1.9 KiB
Systemverilog
72 lines
1.9 KiB
Systemverilog
/* Copyright 2018 ETH Zurich and University of Bologna.
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* Copyright and related rights are licensed under the Solderpad Hardware
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* License, Version 0.51 (the "License"); you may not use this file except in
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* compliance with the License. You may obtain a copy of the License at
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* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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* or agreed to in writing, software, hardware and materials distributed under
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* this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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* CONDITIONS OF ANY KIND, either express or implied. See the License for the
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* specific language governing permissions and limitations under the License.
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*
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* File: $filename.v
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*
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* Description: Auto-generated bootrom
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*/
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// Auto-generated code
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module debug_rom (
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input wire clk_i,
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input wire req_i,
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input wire [63:0] addr_i,
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output wire [63:0] rdata_o
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);
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localparam RomSize = 19;
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wire [RomSize-1:0][63:0] mem;
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assign mem = {
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64'h00000000_7b200073,
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64'h7b202473_7b302573,
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64'h10852423_f1402473,
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64'ha85ff06f_7b202473,
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64'h7b302573_10052223,
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64'h00100073_7b202473,
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64'h7b302573_10052623,
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64'h00c51513_00c55513,
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64'h00000517_fd5ff06f,
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64'hfa041ce3_00247413,
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64'h40044403_00a40433,
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64'hf1402473_02041c63,
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64'h00147413_40044403,
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64'h00a40433_10852023,
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64'hf1402473_00c51513,
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64'h00c55513_00000517,
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64'h7b351073_7b241073,
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64'h0ff0000f_04c0006f,
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64'h07c0006f_00c0006f
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};
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reg [4:0] addr_q;
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always @ (posedge clk_i) begin
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if (req_i) begin
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addr_q <= addr_i[7:3];
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end
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end
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reg[63:0] rdata;
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// this prevents spurious Xes from propagating into
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// the speculative fetch stage of the core
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always @ (*) begin
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rdata = 64'h0;
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if (addr_q < 5'd19) begin
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rdata = mem[addr_q];
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end
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end
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assign rdata_o = rdata;
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endmodule
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