69 lines
2.0 KiB
Verilog
69 lines
2.0 KiB
Verilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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// csr reg module
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module csr_reg(
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input wire clk,
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input wire rst,
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input wire we_i,
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input wire[`MemAddrBus] raddr_i,
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input wire[`MemAddrBus] waddr_i,
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input wire[`RegBus] data_i,
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output reg[`RegBus] data_o
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);
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localparam CSR_CYCLE = 12'hc00;
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localparam CSR_CYCLEH = 12'hc80;
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reg[63:0] cycle;
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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cycle <= 64'h0;
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end else begin
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cycle <= cycle + 1'b1;
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end
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end
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// read reg
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always @ (*) begin
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if (rst == `RstEnable) begin
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data_o <= `ZeroWord;
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end else begin
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case (raddr_i[11:0])
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CSR_CYCLE: begin
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data_o <= cycle[31:0];
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end
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CSR_CYCLEH: begin
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data_o <= cycle[63:32];
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end
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default: begin
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data_o <= `ZeroWord;
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end
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endcase
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end
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end
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endmodule
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