244 lines
8.3 KiB
Systemverilog
244 lines
8.3 KiB
Systemverilog
/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module spi_core #(
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parameter int unsigned TX_FIFO_DEPTH = 8,
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parameter int unsigned RX_FIFO_DEPTH = 8
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)(
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input logic clk_i,
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input logic rst_ni,
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// SPI引脚信号
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input logic spi_clk_i,
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output logic spi_clk_o,
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output logic spi_clk_oe_o,
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input logic spi_ss_i,
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output logic spi_ss_o,
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output logic spi_ss_oe_o,
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input logic spi_dq0_i,
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output logic spi_dq0_o,
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output logic spi_dq0_oe_o,
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input logic spi_dq1_i,
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output logic spi_dq1_o,
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output logic spi_dq1_oe_o,
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input logic spi_dq2_i,
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output logic spi_dq2_o,
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output logic spi_dq2_oe_o,
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input logic spi_dq3_i,
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output logic spi_dq3_o,
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output logic spi_dq3_oe_o,
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// 中断信号
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output logic irq_o,
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// OBI总线接口信号
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input logic reg_we_i,
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input logic reg_re_i,
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input logic [31:0] reg_wdata_i,
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input logic [ 3:0] reg_be_i,
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input logic [31:0] reg_addr_i,
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output logic [31:0] reg_rdata_o
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);
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import spi_reg_pkg::*;
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parameter int unsigned TX_FIFO_ADDR_DEPTH = (TX_FIFO_DEPTH > 1) ? $clog2(TX_FIFO_DEPTH) : 1;
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parameter int unsigned RX_FIFO_ADDR_DEPTH = (RX_FIFO_DEPTH > 1) ? $clog2(RX_FIFO_DEPTH) : 1;
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spi_reg_pkg::spi_reg2hw_t reg2hw;
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spi_reg_pkg::spi_hw2reg_t hw2reg;
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logic [TX_FIFO_ADDR_DEPTH-1:0] tx_fifo_usage;
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logic [RX_FIFO_ADDR_DEPTH-1:0] rx_fifo_usage;
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logic master_enable;
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logic master_start;
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logic master_ready, master_ready_re, master_ready_fe;
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logic master_read;
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logic master_msb_first;
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logic master_data_valid, master_data_valid_re;
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logic master_ss_sw_ctrl;
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logic master_ss_level;
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logic busy_q;
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logic [2:0] master_clk_div;
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logic [1:0] master_cp_mode;
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logic [1:0] master_spi_mode;
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logic [3:0] master_ss_delay_cnt;
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logic [7:0] master_data_out;
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logic tx_fifo_full;
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logic tx_fifo_empty;
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logic [7:0] tx_fifo_data_in;
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logic tx_fifo_push;
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logic [7:0] tx_fifo_data_out;
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logic tx_fifo_pop;
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logic rx_fifo_full;
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logic rx_fifo_empty;
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logic [7:0] rx_fifo_data_in;
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logic rx_fifo_push;
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logic [7:0] rx_fifo_data_out;
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logic rx_fifo_pop;
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assign master_enable = ~reg2hw.ctrl0.role_mode.q;
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assign master_start = reg2hw.ctrl0.enable.q && (!tx_fifo_empty);
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assign master_read = reg2hw.ctrl0.read.q;
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assign master_msb_first = reg2hw.ctrl0.msb_first.q;
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assign master_clk_div = reg2hw.ctrl0.clk_div.q;
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assign master_cp_mode = reg2hw.ctrl0.cp_mode.q;
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assign master_spi_mode = reg2hw.ctrl0.spi_mode.q;
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assign master_ss_delay_cnt = reg2hw.ctrl0.ss_delay.q;
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assign master_ss_sw_ctrl = reg2hw.ctrl0.ss_sw_ctrl.q;
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assign master_ss_level = reg2hw.ctrl0.ss_level.q;
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assign tx_fifo_push = reg2hw.txdata.qe;
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assign tx_fifo_data_in = reg2hw.txdata.q;
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assign tx_fifo_pop = master_data_valid_re | master_ready_fe;
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// 读操作才把接收到的数据压入RX FIFO
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assign rx_fifo_push = master_data_valid_re & master_read;
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assign rx_fifo_data_in = master_data_out;
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assign rx_fifo_pop = reg2hw.rxdata.re;
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assign hw2reg.rxdata.d = rx_fifo_data_out;
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assign hw2reg.status.tx_fifo_full.d = tx_fifo_full;
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assign hw2reg.status.tx_fifo_empty.d = tx_fifo_empty;
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assign hw2reg.status.rx_fifo_full.d = rx_fifo_full;
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assign hw2reg.status.rx_fifo_empty.d = rx_fifo_empty;
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// 传输完成置位中断pending
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assign hw2reg.ctrl0.int_pending.d = 1'b1;
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assign hw2reg.ctrl0.int_pending.de = master_enable & master_ready_re & reg2hw.ctrl0.int_en.q;
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// 传输完成清零busy位
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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busy_q <= 1'b0;
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end else begin
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if (master_start) begin
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busy_q <= 1'b1;
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end else if (master_enable & master_ready_re) begin
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busy_q <= 1'b0;
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end
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end
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end
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assign hw2reg.status.busy.d = busy_q;
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// 中断信号
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assign irq_o = reg2hw.ctrl0.int_pending.q;
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edge_detect #(
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.DP(0)
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) master_data_valid_ed (
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.clk_i(clk_i),
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.rst_ni(rst_ni),
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.sig_i(master_data_valid),
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.sig_o(),
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.re_o(master_data_valid_re),
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.fe_o()
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);
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edge_detect #(
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.DP(0)
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) master_ready_ed (
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.clk_i(clk_i),
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.rst_ni(rst_ni),
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.sig_i(master_ready),
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.sig_o(),
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.re_o(master_ready_re),
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.fe_o(master_ready_fe)
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);
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// TX FIFO
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sync_fifo #(
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.DATA_WIDTH(8),
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.DEPTH(TX_FIFO_DEPTH)
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) u_tx_fifo (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.flush_i (1'b0),
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.testmode_i (1'b0),
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.full_o (tx_fifo_full),
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.empty_o (tx_fifo_empty),
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.usage_o (tx_fifo_usage),
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.data_i (tx_fifo_data_in),
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.push_i (tx_fifo_push),
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.data_o (tx_fifo_data_out),
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.pop_i (tx_fifo_pop)
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);
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// RX FIFO
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sync_fifo #(
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.DATA_WIDTH(8),
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.DEPTH(RX_FIFO_DEPTH)
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) u_rx_fifo (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.flush_i (1'b0),
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.testmode_i (1'b0),
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.full_o (rx_fifo_full),
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.empty_o (rx_fifo_empty),
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.usage_o (rx_fifo_usage),
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.data_i (rx_fifo_data_in),
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.push_i (rx_fifo_push),
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.data_o (rx_fifo_data_out),
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.pop_i (rx_fifo_pop)
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);
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spi_master u_spi_master (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.start_i (master_start),
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.read_i (master_read),
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.data_i (tx_fifo_data_out),
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.spi_mode_i (master_spi_mode),
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.cp_mode_i (master_cp_mode),
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.div_ratio_i (master_clk_div),
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.msb_first_i (master_msb_first),
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.ss_delay_cnt_i(master_ss_delay_cnt),
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.ss_sw_ctrl_i (master_ss_sw_ctrl),
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.ss_level_i (master_ss_level),
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.data_o (master_data_out),
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.ready_o (master_ready),
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.data_valid_o (master_data_valid),
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.spi_clk_o (spi_clk_o),
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.spi_clk_oe_o (spi_clk_oe_o),
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.spi_ss_o (spi_ss_o),
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.spi_ss_oe_o (spi_ss_oe_o),
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.spi_dq0_i (spi_dq0_i),
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.spi_dq0_o (spi_dq0_o),
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.spi_dq0_oe_o (spi_dq0_oe_o),
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.spi_dq1_i (spi_dq1_i),
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.spi_dq1_o (spi_dq1_o),
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.spi_dq1_oe_o (spi_dq1_oe_o),
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.spi_dq2_i (spi_dq2_i),
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.spi_dq2_o (spi_dq2_o),
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.spi_dq2_oe_o (spi_dq2_oe_o),
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.spi_dq3_i (spi_dq3_i),
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.spi_dq3_o (spi_dq3_o),
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.spi_dq3_oe_o (spi_dq3_oe_o)
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);
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spi_reg_top u_spi_reg_top (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.reg2hw (reg2hw),
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.hw2reg (hw2reg),
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.reg_we (reg_we_i),
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.reg_re (reg_re_i),
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.reg_wdata (reg_wdata_i),
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.reg_be (reg_be_i),
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.reg_addr (reg_addr_i),
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.reg_rdata (reg_rdata_o)
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);
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endmodule
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