44 lines
1.5 KiB
Systemverilog
44 lines
1.5 KiB
Systemverilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.sv"
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// 复位控制模块
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module rst_gen #(
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parameter RESET_FIFO_DEPTH = 5
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)(
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input wire clk,
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input wire rst_ni,
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output wire rst_no
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);
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reg[RESET_FIFO_DEPTH-1:0] synch_regs_q;
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always @ (posedge clk or negedge rst_ni) begin
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if (~rst_ni) begin
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synch_regs_q <= 0;
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end else begin
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synch_regs_q <= {synch_regs_q[RESET_FIFO_DEPTH-2:0], 1'b1};
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end
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end
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assign rst_no = synch_regs_q[RESET_FIFO_DEPTH-1];
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endmodule
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