155 lines
3.8 KiB
Systemverilog
155 lines
3.8 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Register Package auto-generated by `reggen` containing data structure
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package uart_reg_pkg;
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// Address widths within the block
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parameter int BlockAw = 4;
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////////////////////////////
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// Typedefs for registers //
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////////////////////////////
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typedef struct packed {
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struct packed {
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logic q;
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logic qe;
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} tx_en;
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struct packed {
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logic q;
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logic qe;
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} rx_en;
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struct packed {
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logic q;
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logic qe;
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} tx_fifo_empty_int_en;
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struct packed {
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logic q;
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logic qe;
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} rx_fifo_not_empty_int_en;
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struct packed {
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logic q;
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logic qe;
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} tx_fifo_rst;
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struct packed {
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logic q;
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logic qe;
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} rx_fifo_rst;
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struct packed {
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logic [15:0] q;
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logic qe;
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} baud_div;
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} uart_reg2hw_ctrl_reg_t;
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typedef struct packed {
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struct packed {
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logic q;
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logic re;
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} txfull;
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struct packed {
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logic q;
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logic re;
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} rxfull;
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struct packed {
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logic q;
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logic re;
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} txempty;
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struct packed {
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logic q;
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logic re;
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} rxempty;
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struct packed {
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logic q;
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logic re;
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} txidle;
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struct packed {
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logic q;
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logic re;
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} rxidle;
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} uart_reg2hw_status_reg_t;
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typedef struct packed {
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logic [7:0] q;
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logic qe;
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} uart_reg2hw_txdata_reg_t;
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typedef struct packed {
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logic [7:0] q;
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logic re;
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} uart_reg2hw_rxdata_reg_t;
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typedef struct packed {
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struct packed {
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logic d;
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} txfull;
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struct packed {
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logic d;
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} rxfull;
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struct packed {
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logic d;
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} txempty;
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struct packed {
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logic d;
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} rxempty;
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struct packed {
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logic d;
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} txidle;
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struct packed {
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logic d;
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} rxidle;
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} uart_hw2reg_status_reg_t;
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typedef struct packed {
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logic [7:0] d;
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} uart_hw2reg_rxdata_reg_t;
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// Register -> HW type
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typedef struct packed {
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uart_reg2hw_ctrl_reg_t ctrl; // [58:30]
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uart_reg2hw_status_reg_t status; // [29:18]
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uart_reg2hw_txdata_reg_t txdata; // [17:9]
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uart_reg2hw_rxdata_reg_t rxdata; // [8:0]
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} uart_reg2hw_t;
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// HW -> register type
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typedef struct packed {
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uart_hw2reg_status_reg_t status; // [13:8]
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uart_hw2reg_rxdata_reg_t rxdata; // [7:0]
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} uart_hw2reg_t;
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// Register offsets
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parameter logic [BlockAw-1:0] UART_CTRL_OFFSET = 4'h0;
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parameter logic [BlockAw-1:0] UART_STATUS_OFFSET = 4'h4;
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parameter logic [BlockAw-1:0] UART_TXDATA_OFFSET = 4'h8;
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parameter logic [BlockAw-1:0] UART_RXDATA_OFFSET = 4'hc;
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// Reset values for hwext registers and their fields
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parameter logic [5:0] UART_STATUS_RESVAL = 6'h3c;
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parameter logic [0:0] UART_STATUS_TXEMPTY_RESVAL = 1'h1;
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parameter logic [0:0] UART_STATUS_RXEMPTY_RESVAL = 1'h1;
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parameter logic [0:0] UART_STATUS_TXIDLE_RESVAL = 1'h1;
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parameter logic [0:0] UART_STATUS_RXIDLE_RESVAL = 1'h1;
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parameter logic [7:0] UART_RXDATA_RESVAL = 8'h0;
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// Register index
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typedef enum int {
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UART_CTRL,
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UART_STATUS,
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UART_TXDATA,
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UART_RXDATA
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} uart_id_e;
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// Register width information to check illegal writes
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parameter logic [3:0] UART_PERMIT [4] = '{
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4'b1111, // index[0] UART_CTRL
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4'b0001, // index[1] UART_STATUS
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4'b0001, // index[2] UART_TXDATA
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4'b0001 // index[3] UART_RXDATA
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};
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endpackage
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