83 lines
3.2 KiB
Systemverilog
83 lines
3.2 KiB
Systemverilog
/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module uart_tx (
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input logic clk_i, // 时钟输入
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input logic rst_ni, // 异步复位信号，低电平有效
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input logic enable_i, // TX模块使能信号
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input logic parity_en_i, // 校验使能
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input logic parity_i, // 校验方式：奇校验还是偶检验
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input logic we_i, // 开始发送数据
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input logic [7:0] wdata_i, // 要发送的一个字节数据
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input logic [15:0] div_ratio_i, // 波特率分频系数
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output logic idle_o, // TX模块空闲
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output logic tx_bit_o // 要发送的1 bit数据
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);
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logic [3:0] bit_cnt_d, bit_cnt_q;
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logic [10:0] shift_reg_d, shift_reg_q;
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logic tx_d, tx_q;
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logic tick;
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always_comb begin
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if (!enable_i) begin
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bit_cnt_d = 4'h0;
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shift_reg_d = 11'h7ff;
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tx_d = 1'b1;
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end else begin
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bit_cnt_d = bit_cnt_q;
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shift_reg_d = shift_reg_q;
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tx_d = tx_q;
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if (we_i) begin
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// LSB first
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shift_reg_d = {1'b1, (parity_en_i ? parity_i : 1'b1), wdata_i, 1'b0};
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bit_cnt_d = (parity_en_i ? 4'd11 : 4'd10);
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end else if ((bit_cnt_q != 4'h0) && tick) begin
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// 右移1位
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shift_reg_d = {1'b1, shift_reg_q[10:1]};
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tx_d = shift_reg_q[0];
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bit_cnt_d = bit_cnt_q - 4'h1;
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end
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end
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end
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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bit_cnt_q <= 4'h0;
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shift_reg_q <= 11'h7ff;
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tx_q <= 1'b1;
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end else begin
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bit_cnt_q <= bit_cnt_d;
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shift_reg_q <= shift_reg_d;
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tx_q <= tx_d;
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end
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end
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assign idle_o = (bit_cnt_q == 4'h0);
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assign tx_bit_o = tx_q;
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clk_div #(
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.RATIO_WIDTH(16)
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) u_clk_div (
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.clk_i(clk_i),
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.rst_ni(rst_ni || (~we_i)),
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.en_i(we_i || (bit_cnt_q != 4'h0)),
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.ratio_i(div_ratio_i),
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.clk_o(tick)
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);
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endmodule
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