305 lines
11 KiB
Systemverilog
305 lines
11 KiB
Systemverilog
/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.sv"
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`define CAUSE_IRQ_EXTERNAL_M {1'b1, 31'd11}
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`define CAUSE_IRQ_SOFTWARE_M {1'b1, 31'd3}
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`define CAUSE_IRQ_TIMER_M {1'b1, 31'd7}
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`define CAUSE_EXCEP_ECALL_M {1'b0, 31'd11}
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`define CAUSE_EXCEP_EBREAK_M {1'b0, 31'd3}
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`define MIE_MTIE_BIT 7
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`define MIE_MEIE_BIT 11
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`define MIE_MSIE_BIT 3
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`define DCSR_CAUSE_NONE 3'h0
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`define DCSR_CAUSE_STEP 3'h4
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`define DCSR_CAUSE_DBGREQ 3'h3
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`define DCSR_CAUSE_EBREAK 3'h1
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module exception (
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input wire clk,
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input wire rst_n,
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input wire inst_valid_i,
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input wire inst_ecall_i, // ecall指令
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input wire inst_ebreak_i, // ebreak指令
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input wire inst_mret_i, // mret指令
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input wire inst_dret_i, // dret指令
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input wire[31:0] inst_addr_i, // 指令地址
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input wire[31:0] mtvec_i, // mtvec寄存器
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input wire[31:0] mepc_i, // mepc寄存器
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input wire[31:0] mstatus_i, // mstatus寄存器
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input wire[31:0] mie_i, // mie寄存器
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input wire[31:0] dpc_i, // dpc寄存器
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input wire[31:0] dcsr_i, // dcsr寄存器
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input wire irq_software_i,
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input wire irq_timer_i,
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input wire irq_external_i,
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input wire[14:0] irq_fast_i,
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input wire[31:0] debug_halt_addr_i,
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input wire debug_req_i,
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output wire csr_we_o, // 写CSR寄存器标志
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output wire[31:0] csr_waddr_o, // 写CSR寄存器地址
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output wire[31:0] csr_wdata_o, // 写CSR寄存器数据
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output wire stall_flag_o, // 流水线暂停标志
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output wire[31:0] int_addr_o, // 中断入口地址
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output wire int_assert_o // 中断标志
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);
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localparam ILLEGAL_INSTR_OFFSET = 0;
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localparam INSTR_ADDR_MISA_OFFSET = 4;
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localparam ECALL_OFFSET = 8;
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localparam EBREAK_OFFSET = 12;
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localparam LOAD_MISA_OFFSET = 16;
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localparam STORE_MISA_OFFSET = 20;
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localparam RESERVED1_EXCEPTION_OFFSET = 24;
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localparam RESERVED2_EXCEPTION_OFFSET = 28;
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localparam EXTERNAL_INT_OFFSET = 32;
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localparam SOFTWARE_INT_OFFSET = 36;
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localparam TIMER_INT_OFFSET = 40;
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localparam FAST_INT_OFFSET = 44;
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localparam S_IDLE = 4'b0001;
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localparam S_W_MEPC = 4'b0010;
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localparam S_W_DCSR = 4'b0100;
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localparam S_ASSERT = 4'b1000;
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reg debug_mode_d, debug_mode_q;
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reg[3:0] state_d, state_q;
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reg[31:0] assert_addr_d, assert_addr_q;
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reg[31:0] return_addr_d, return_addr_q;
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reg csr_we;
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reg[31:0] csr_waddr;
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reg[31:0] csr_wdata;
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wire global_int_en;
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assign global_int_en = mstatus_i[3];
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reg[3:0] fast_irq_id;
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wire fast_irq_req;
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always @ (*) begin
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if (irq_fast_i[ 0]) fast_irq_id = 4'd0;
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else if (irq_fast_i[ 1]) fast_irq_id = 4'd1;
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else if (irq_fast_i[ 2]) fast_irq_id = 4'd2;
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else if (irq_fast_i[ 3]) fast_irq_id = 4'd3;
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else if (irq_fast_i[ 4]) fast_irq_id = 4'd4;
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else if (irq_fast_i[ 5]) fast_irq_id = 4'd5;
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else if (irq_fast_i[ 6]) fast_irq_id = 4'd6;
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else if (irq_fast_i[ 7]) fast_irq_id = 4'd7;
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else if (irq_fast_i[ 8]) fast_irq_id = 4'd8;
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else if (irq_fast_i[ 9]) fast_irq_id = 4'd9;
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else if (irq_fast_i[10]) fast_irq_id = 4'd10;
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else if (irq_fast_i[11]) fast_irq_id = 4'd11;
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else if (irq_fast_i[12]) fast_irq_id = 4'd12;
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else if (irq_fast_i[13]) fast_irq_id = 4'd13;
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else fast_irq_id = 4'd14;
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end
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assign fast_irq_req = |irq_fast_i;
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reg interrupt_req_tmp;
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reg[31:0] interrupt_cause;
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reg[31:0] interrupt_offset;
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wire interrupt_req = inst_valid_i & interrupt_req_tmp;
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always @ (*) begin
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if (fast_irq_req) begin
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interrupt_req_tmp = 1'b1;
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interrupt_cause = {1'b1, {26{1'b0}}, 1'b1, fast_irq_id};
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interrupt_offset = {fast_irq_id, 2'b0} + FAST_INT_OFFSET;
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end else if (irq_external_i & mie_i[`MIE_MEIE_BIT]) begin
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interrupt_req_tmp = 1'b1;
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interrupt_cause = `CAUSE_IRQ_EXTERNAL_M;
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interrupt_offset = EXTERNAL_INT_OFFSET;
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end else if (irq_software_i & mie_i[`MIE_MSIE_BIT]) begin
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interrupt_req_tmp = 1'b1;
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interrupt_cause = `CAUSE_IRQ_SOFTWARE_M;
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interrupt_offset = SOFTWARE_INT_OFFSET;
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end else if (irq_timer_i & mie_i[`MIE_MTIE_BIT]) begin
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interrupt_req_tmp = 1'b1;
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interrupt_cause = `CAUSE_IRQ_TIMER_M;
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interrupt_offset = TIMER_INT_OFFSET;
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end else begin
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interrupt_req_tmp = 1'b0;
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interrupt_cause = 32'h0;
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interrupt_offset = 32'h0;
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end
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end
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reg exception_req;
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reg[31:0] exception_cause;
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reg[31:0] exception_offset;
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always @ (*) begin
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if (inst_ecall_i) begin
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exception_req = 1'b1;
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exception_cause = `CAUSE_EXCEP_ECALL_M;
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exception_offset = ECALL_OFFSET;
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end else if (inst_ebreak_i & (!dcsr_i[15]) & (~debug_mode_q)) begin
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exception_req = 1'b1;
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exception_cause = `CAUSE_EXCEP_EBREAK_M;
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exception_offset = EBREAK_OFFSET;
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end else begin
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exception_req = 1'b0;
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exception_cause = 32'h0;
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exception_offset = 32'h0;
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end
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end
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wire int_or_exception_req;
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wire[31:0] int_or_exception_cause;
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wire[31:0] int_or_exception_offset;
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assign int_or_exception_req = (interrupt_req & global_int_en) | exception_req;
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assign int_or_exception_cause = exception_req ? exception_cause : interrupt_cause;
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assign int_or_exception_offset = exception_req ? exception_offset : interrupt_offset;
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reg enter_debug_cause_debugger_req;
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reg enter_debug_cause_single_step;
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reg enter_debug_cause_ebreak;
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reg[2:0] dcsr_cause_d, dcsr_cause_q;
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always @ (*) begin
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enter_debug_cause_debugger_req = 1'b0;
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enter_debug_cause_single_step = 1'b0;
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enter_debug_cause_ebreak = 1'b0;
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dcsr_cause_d = `DCSR_CAUSE_NONE;
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if (inst_ebreak_i & debug_mode_q) begin
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enter_debug_cause_ebreak = 1'b1;
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dcsr_cause_d = `DCSR_CAUSE_EBREAK;
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end else if ((~debug_mode_q) & debug_req_i & inst_valid_i) begin
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enter_debug_cause_debugger_req = 1'b1;
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dcsr_cause_d = `DCSR_CAUSE_DBGREQ;
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end else if (inst_ebreak_i & dcsr_i[15]) begin
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enter_debug_cause_single_step = 1'b1;
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dcsr_cause_d = `DCSR_CAUSE_STEP;
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end
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end
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wire debug_mode_req = enter_debug_cause_debugger_req |
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enter_debug_cause_single_step |
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enter_debug_cause_ebreak;
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assign stall_flag_o = ((state_q != S_IDLE) & (state_q != S_ASSERT)) |
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(interrupt_req & global_int_en) | exception_req |
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debug_mode_req |
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inst_mret_i |
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inst_dret_i;
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always @ (*) begin
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state_d = state_q;
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assert_addr_d = assert_addr_q;
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debug_mode_d = debug_mode_q;
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return_addr_d = return_addr_q;
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csr_we = 1'b0;
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csr_waddr = 32'h0;
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csr_wdata = 32'h0;
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case (state_q)
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S_IDLE: begin
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if (int_or_exception_req) begin
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csr_we = 1'b1;
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csr_waddr = {20'h0, `CSR_MCAUSE};
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csr_wdata = int_or_exception_cause;
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assert_addr_d = mtvec_i + int_or_exception_offset;
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return_addr_d = inst_addr_i;
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state_d = S_W_MEPC;
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end else if (debug_mode_req) begin
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debug_mode_d = 1'b1;
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if (enter_debug_cause_debugger_req) begin
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csr_we = 1'b1;
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csr_waddr = {20'h0, `CSR_DPC};
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csr_wdata = inst_addr_i;
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end
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assert_addr_d = debug_halt_addr_i;
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state_d = S_W_DCSR;
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end else if (inst_mret_i) begin
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assert_addr_d = mepc_i;
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state_d = S_ASSERT;
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end else if (inst_dret_i) begin
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assert_addr_d = dpc_i;
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state_d = S_ASSERT;
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debug_mode_d = 1'b0;
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end
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end
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S_W_MEPC: begin
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csr_we = 1'b1;
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csr_waddr = {20'h0, `CSR_MEPC};
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csr_wdata = return_addr_q;
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state_d = S_ASSERT;
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end
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S_W_DCSR: begin
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csr_we = 1'b1;
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csr_waddr = {20'h0, `CSR_DCSR};
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csr_wdata = {dcsr_i[31:9], dcsr_cause_q, dcsr_i[5:0]};
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state_d = S_ASSERT;
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end
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S_ASSERT: begin
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csr_we = 1'b0;
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state_d = S_IDLE;
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end
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default:;
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endcase
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end
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assign csr_we_o = csr_we;
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assign csr_waddr_o = csr_waddr;
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assign csr_wdata_o = csr_wdata;
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assign int_assert_o = (state_q == S_ASSERT);
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assign int_addr_o = assert_addr_q;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state_q <= S_IDLE;
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assert_addr_q <= 32'h0;
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debug_mode_q <= 1'b0;
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return_addr_q <= 32'h0;
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dcsr_cause_q <= `DCSR_CAUSE_NONE;
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end else begin
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state_q <= state_d;
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assert_addr_q <= assert_addr_d;
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debug_mode_q <= debug_mode_d;
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return_addr_q <= return_addr_d;
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dcsr_cause_q <= dcsr_cause_d;
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end
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end
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endmodule
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