72 lines
1.8 KiB
Plaintext
72 lines
1.8 KiB
Plaintext
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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{ name: "flash_ctrl",
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clocking: [{clock: "clk_i", reset: "rst_ni"}],
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bus_interfaces: [
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{ protocol: "tlul", direction: "device" }
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],
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regwidth: "32",
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registers: [
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{ name: "CTRL",
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desc: "flash_ctrl control register",
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swaccess: "rw",
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hwaccess: "hrw",
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hwqe: "true",
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fields: [
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{ bits: "0",
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name: "START",
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desc: "start read or write",
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}
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{ bits: "2:1",
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name: "OP_MODE",
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desc: "0: read, 1: program, 2: erase, 3: qspi init",
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}
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{ bits: "3",
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name: "SW_CTRL",
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desc: "0: hardware ctrl, 1: software ctrl",
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}
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{ bits: "4",
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name: "PROGRAM_INIT",
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desc: "0: not program, 1: prepare for program",
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}
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{ bits: "5",
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name: "WRITE_ERROR",
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swaccess: "ro",
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desc: "0: write succ, 1: write error",
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}
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{ bits: "31:6",
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swaccess: "r0w1c",
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name: "RESERVED",
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desc: "reserved, not use",
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}
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]
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}
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{ name: "ADDR",
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desc: "flash_ctrl address register",
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swaccess: "rw",
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hwaccess: "hro",
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fields: [
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{ bits: "22:0",
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name: "RW_ADDRESS",
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desc: "read or write address",
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}
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{ bits: "31:23",
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swaccess: "r0w1c",
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name: "RESERVED",
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desc: "reserved, not use",
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}
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]
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}
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{ name: "DATA",
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desc: "flash_ctrl data register",
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swaccess: "rw",
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hwaccess: "hrw",
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fields: [
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{ bits: "31:0",
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}
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]
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}
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]
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}
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