376 lines
8.5 KiB
Systemverilog
376 lines
8.5 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Register Top module auto-generated by `reggen`
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module flash_ctrl_reg_top (
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input logic clk_i,
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input logic rst_ni,
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// To HW
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output flash_ctrl_reg_pkg::flash_ctrl_reg2hw_t reg2hw, // Write
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input flash_ctrl_reg_pkg::flash_ctrl_hw2reg_t hw2reg, // Read
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input logic reg_we,
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input logic reg_re,
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input logic [31:0] reg_wdata,
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input logic [ 3:0] reg_be,
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input logic [31:0] reg_addr,
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output logic [31:0] reg_rdata
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);
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import flash_ctrl_reg_pkg::* ;
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localparam int AW = 4;
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localparam int DW = 32;
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localparam int DBW = DW/8; // Byte Width
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logic reg_error;
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logic addrmiss, wr_err;
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logic [DW-1:0] reg_rdata_next;
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assign reg_rdata = reg_rdata_next;
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assign reg_error = wr_err;
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// Define SW related signals
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// Format: <reg>_<field>_{wd|we|qs}
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// or <reg>_{wd|we|qs} if field == 1 or 0
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logic ctrl_we;
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logic ctrl_start_qs;
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logic ctrl_start_wd;
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logic [1:0] ctrl_op_mode_qs;
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logic [1:0] ctrl_op_mode_wd;
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logic ctrl_sw_ctrl_qs;
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logic ctrl_sw_ctrl_wd;
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logic ctrl_program_init_qs;
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logic ctrl_program_init_wd;
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logic ctrl_write_error_qs;
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logic [25:0] ctrl_reserved_wd;
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logic addr_we;
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logic [22:0] addr_rw_address_qs;
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logic [22:0] addr_rw_address_wd;
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logic [8:0] addr_reserved_wd;
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logic data_we;
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logic [31:0] data_qs;
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logic [31:0] data_wd;
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// Register instances
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// R[ctrl]: V(False)
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// F[start]: 0:0
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prim_subreg #(
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.DW (1),
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.SWACCESS("RW"),
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.RESVAL (1'h0)
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) u_ctrl_start (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_start_wd),
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// from internal hardware
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.de (hw2reg.ctrl.start.de),
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.d (hw2reg.ctrl.start.d),
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// to internal hardware
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.qe (reg2hw.ctrl.start.qe),
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.q (reg2hw.ctrl.start.q),
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// to register interface (read)
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.qs (ctrl_start_qs)
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);
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// F[op_mode]: 2:1
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prim_subreg #(
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.DW (2),
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.SWACCESS("RW"),
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.RESVAL (2'h0)
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) u_ctrl_op_mode (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_op_mode_wd),
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// from internal hardware
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.de (hw2reg.ctrl.op_mode.de),
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.d (hw2reg.ctrl.op_mode.d),
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// to internal hardware
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.qe (reg2hw.ctrl.op_mode.qe),
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.q (reg2hw.ctrl.op_mode.q),
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// to register interface (read)
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.qs (ctrl_op_mode_qs)
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);
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// F[sw_ctrl]: 3:3
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prim_subreg #(
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.DW (1),
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.SWACCESS("RW"),
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.RESVAL (1'h0)
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) u_ctrl_sw_ctrl (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_sw_ctrl_wd),
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// from internal hardware
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.de (hw2reg.ctrl.sw_ctrl.de),
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.d (hw2reg.ctrl.sw_ctrl.d),
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// to internal hardware
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.qe (reg2hw.ctrl.sw_ctrl.qe),
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.q (reg2hw.ctrl.sw_ctrl.q),
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// to register interface (read)
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.qs (ctrl_sw_ctrl_qs)
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);
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// F[program_init]: 4:4
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prim_subreg #(
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.DW (1),
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.SWACCESS("RW"),
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.RESVAL (1'h0)
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) u_ctrl_program_init (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_program_init_wd),
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// from internal hardware
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.de (hw2reg.ctrl.program_init.de),
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.d (hw2reg.ctrl.program_init.d),
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// to internal hardware
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.qe (reg2hw.ctrl.program_init.qe),
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.q (reg2hw.ctrl.program_init.q),
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// to register interface (read)
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.qs (ctrl_program_init_qs)
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);
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// F[write_error]: 5:5
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prim_subreg #(
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.DW (1),
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.SWACCESS("RO"),
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.RESVAL (1'h0)
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) u_ctrl_write_error (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (1'b0),
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.wd ('0),
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// from internal hardware
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.de (hw2reg.ctrl.write_error.de),
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.d (hw2reg.ctrl.write_error.d),
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// to internal hardware
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.qe (reg2hw.ctrl.write_error.qe),
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.q (reg2hw.ctrl.write_error.q),
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// to register interface (read)
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.qs (ctrl_write_error_qs)
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);
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// F[reserved]: 31:6
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prim_subreg #(
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.DW (26),
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.SWACCESS("W1C"),
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.RESVAL (26'h0)
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) u_ctrl_reserved (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_reserved_wd),
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// from internal hardware
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.de (hw2reg.ctrl.reserved.de),
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.d (hw2reg.ctrl.reserved.d),
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// to internal hardware
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.qe (reg2hw.ctrl.reserved.qe),
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.q (reg2hw.ctrl.reserved.q),
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// to register interface (read)
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.qs ()
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);
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// R[addr]: V(False)
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// F[rw_address]: 22:0
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prim_subreg #(
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.DW (23),
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.SWACCESS("RW"),
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.RESVAL (23'h0)
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) u_addr_rw_address (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (addr_we),
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.wd (addr_rw_address_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.addr.rw_address.q),
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// to register interface (read)
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.qs (addr_rw_address_qs)
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);
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// F[reserved]: 31:23
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prim_subreg #(
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.DW (9),
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.SWACCESS("W1C"),
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.RESVAL (9'h0)
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) u_addr_reserved (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (addr_we),
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.wd (addr_reserved_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.addr.reserved.q),
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// to register interface (read)
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.qs ()
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);
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// R[data]: V(False)
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prim_subreg #(
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.DW (32),
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.SWACCESS("RW"),
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.RESVAL (32'h0)
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) u_data (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (data_we),
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.wd (data_wd),
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// from internal hardware
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.de (hw2reg.data.de),
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.d (hw2reg.data.d),
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// to internal hardware
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.qe (),
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.q (reg2hw.data.q),
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// to register interface (read)
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.qs (data_qs)
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);
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logic [2:0] addr_hit;
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always_comb begin
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addr_hit = '0;
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addr_hit[0] = (reg_addr == FLASH_CTRL_CTRL_OFFSET);
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addr_hit[1] = (reg_addr == FLASH_CTRL_ADDR_OFFSET);
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addr_hit[2] = (reg_addr == FLASH_CTRL_DATA_OFFSET);
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end
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assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
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// Check sub-word write is permitted
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always_comb begin
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wr_err = (reg_we &
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((addr_hit[0] & (|(FLASH_CTRL_PERMIT[0] & ~reg_be))) |
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(addr_hit[1] & (|(FLASH_CTRL_PERMIT[1] & ~reg_be))) |
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(addr_hit[2] & (|(FLASH_CTRL_PERMIT[2] & ~reg_be)))));
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end
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assign ctrl_we = addr_hit[0] & reg_we & !reg_error;
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assign ctrl_start_wd = reg_wdata[0];
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assign ctrl_op_mode_wd = reg_wdata[2:1];
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assign ctrl_sw_ctrl_wd = reg_wdata[3];
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assign ctrl_program_init_wd = reg_wdata[4];
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assign ctrl_reserved_wd = reg_wdata[31:6];
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assign addr_we = addr_hit[1] & reg_we & !reg_error;
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assign addr_rw_address_wd = reg_wdata[22:0];
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assign addr_reserved_wd = reg_wdata[31:23];
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assign data_we = addr_hit[2] & reg_we & !reg_error;
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assign data_wd = reg_wdata[31:0];
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// Read data return
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always_comb begin
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reg_rdata_next = '0;
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unique case (1'b1)
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addr_hit[0]: begin
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reg_rdata_next[0] = ctrl_start_qs;
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reg_rdata_next[2:1] = ctrl_op_mode_qs;
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reg_rdata_next[3] = ctrl_sw_ctrl_qs;
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reg_rdata_next[4] = ctrl_program_init_qs;
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reg_rdata_next[5] = ctrl_write_error_qs;
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reg_rdata_next[31:6] = '0;
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end
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addr_hit[1]: begin
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reg_rdata_next[22:0] = addr_rw_address_qs;
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reg_rdata_next[31:23] = '0;
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end
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addr_hit[2]: begin
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reg_rdata_next[31:0] = data_qs;
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end
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default: begin
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reg_rdata_next = '1;
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end
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endcase
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end
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// Unused signal tieoff
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// wdata / byte enable are not always fully used
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// add a blanket unused statement to handle lint waivers
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logic unused_wdata;
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logic unused_be;
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assign unused_wdata = ^reg_wdata;
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assign unused_be = ^reg_be;
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endmodule
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