80 lines
2.6 KiB
Systemverilog
80 lines
2.6 KiB
Systemverilog
/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module flash_ctrl_top (
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input logic clk_i,
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input logic rst_ni,
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// SPI引脚信号
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output logic spi_clk_o,
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output logic spi_clk_oe_o,
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output logic spi_ss_o,
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output logic spi_ss_oe_o,
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input logic spi_dq0_i,
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output logic spi_dq0_o,
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output logic spi_dq0_oe_o,
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input logic spi_dq1_i,
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output logic spi_dq1_o,
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output logic spi_dq1_oe_o,
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input logic spi_dq2_i,
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output logic spi_dq2_o,
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output logic spi_dq2_oe_o,
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input logic spi_dq3_i,
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output logic spi_dq3_o,
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output logic spi_dq3_oe_o,
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// OBI总线接口信号
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input logic req_i,
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input logic we_i,
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input logic [ 3:0] be_i,
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input logic [31:0] addr_i,
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input logic [31:0] data_i,
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output logic gnt_o,
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output logic rvalid_o,
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output logic [31:0] data_o
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);
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flash_ctrl_core u_flash_ctrl_core (
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.clk_i,
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.rst_ni,
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.spi_clk_o,
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.spi_clk_oe_o,
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.spi_ss_o,
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.spi_ss_oe_o,
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.spi_dq0_i,
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.spi_dq0_o,
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.spi_dq0_oe_o,
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.spi_dq1_i,
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.spi_dq1_o,
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.spi_dq1_oe_o,
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.spi_dq2_i,
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.spi_dq2_o,
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.spi_dq2_oe_o,
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.spi_dq3_i,
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.spi_dq3_o,
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.spi_dq3_oe_o,
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.req_i,
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.we_i,
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.be_i,
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.addr_i,
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.data_i,
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.gnt_o,
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.rvalid_o,
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.data_o
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);
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endmodule
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