580 lines
12 KiB
Systemverilog
580 lines
12 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Register Top module auto-generated by `reggen`
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module pinmux_reg_top (
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input logic clk_i,
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input logic rst_ni,
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// To HW
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output pinmux_reg_pkg::pinmux_reg2hw_t reg2hw, // Write
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input logic reg_we,
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input logic reg_re,
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input logic [31:0] reg_wdata,
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input logic [ 3:0] reg_be,
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input logic [31:0] reg_addr,
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output logic [31:0] reg_rdata
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);
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import pinmux_reg_pkg::* ;
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localparam int AW = 2;
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localparam int DW = 32;
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localparam int DBW = DW/8; // Byte Width
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logic reg_error;
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logic addrmiss, wr_err;
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logic [DW-1:0] reg_rdata_next;
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assign reg_rdata = reg_rdata_next;
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assign reg_error = wr_err;
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// Define SW related signals
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// Format: <reg>_<field>_{wd|we|qs}
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// or <reg>_{wd|we|qs} if field == 1 or 0
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logic ctrl_we;
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logic [1:0] ctrl_io0_mux_qs;
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logic [1:0] ctrl_io0_mux_wd;
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logic [1:0] ctrl_io1_mux_qs;
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logic [1:0] ctrl_io1_mux_wd;
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logic [1:0] ctrl_io2_mux_qs;
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logic [1:0] ctrl_io2_mux_wd;
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logic [1:0] ctrl_io3_mux_qs;
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logic [1:0] ctrl_io3_mux_wd;
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logic [1:0] ctrl_io4_mux_qs;
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logic [1:0] ctrl_io4_mux_wd;
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logic [1:0] ctrl_io5_mux_qs;
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logic [1:0] ctrl_io5_mux_wd;
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logic [1:0] ctrl_io6_mux_qs;
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logic [1:0] ctrl_io6_mux_wd;
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logic [1:0] ctrl_io7_mux_qs;
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logic [1:0] ctrl_io7_mux_wd;
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logic [1:0] ctrl_io8_mux_qs;
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logic [1:0] ctrl_io8_mux_wd;
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logic [1:0] ctrl_io9_mux_qs;
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logic [1:0] ctrl_io9_mux_wd;
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logic [1:0] ctrl_io10_mux_qs;
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logic [1:0] ctrl_io10_mux_wd;
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logic [1:0] ctrl_io11_mux_qs;
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logic [1:0] ctrl_io11_mux_wd;
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logic [1:0] ctrl_io12_mux_qs;
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logic [1:0] ctrl_io12_mux_wd;
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logic [1:0] ctrl_io13_mux_qs;
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logic [1:0] ctrl_io13_mux_wd;
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logic [1:0] ctrl_io14_mux_qs;
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logic [1:0] ctrl_io14_mux_wd;
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logic [1:0] ctrl_io15_mux_qs;
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logic [1:0] ctrl_io15_mux_wd;
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// Register instances
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// R[ctrl]: V(False)
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// F[io0_mux]: 1:0
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prim_subreg #(
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.DW (2),
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.SWACCESS("RW"),
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.RESVAL (2'h0)
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) u_ctrl_io0_mux (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_io0_mux_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.ctrl.io0_mux.q),
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// to register interface (read)
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.qs (ctrl_io0_mux_qs)
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);
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// F[io1_mux]: 3:2
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prim_subreg #(
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.DW (2),
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.SWACCESS("RW"),
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.RESVAL (2'h0)
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) u_ctrl_io1_mux (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_io1_mux_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.ctrl.io1_mux.q),
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// to register interface (read)
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.qs (ctrl_io1_mux_qs)
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);
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// F[io2_mux]: 5:4
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prim_subreg #(
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.DW (2),
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.SWACCESS("RW"),
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.RESVAL (2'h0)
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) u_ctrl_io2_mux (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_io2_mux_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.ctrl.io2_mux.q),
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// to register interface (read)
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.qs (ctrl_io2_mux_qs)
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);
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// F[io3_mux]: 7:6
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prim_subreg #(
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.DW (2),
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.SWACCESS("RW"),
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.RESVAL (2'h0)
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) u_ctrl_io3_mux (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_io3_mux_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.ctrl.io3_mux.q),
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// to register interface (read)
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.qs (ctrl_io3_mux_qs)
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);
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// F[io4_mux]: 9:8
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prim_subreg #(
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.DW (2),
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.SWACCESS("RW"),
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.RESVAL (2'h0)
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) u_ctrl_io4_mux (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_io4_mux_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.ctrl.io4_mux.q),
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// to register interface (read)
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.qs (ctrl_io4_mux_qs)
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);
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// F[io5_mux]: 11:10
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prim_subreg #(
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.DW (2),
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.SWACCESS("RW"),
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.RESVAL (2'h0)
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) u_ctrl_io5_mux (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_io5_mux_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.ctrl.io5_mux.q),
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// to register interface (read)
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.qs (ctrl_io5_mux_qs)
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);
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// F[io6_mux]: 13:12
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prim_subreg #(
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.DW (2),
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.SWACCESS("RW"),
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.RESVAL (2'h0)
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) u_ctrl_io6_mux (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_io6_mux_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.ctrl.io6_mux.q),
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// to register interface (read)
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.qs (ctrl_io6_mux_qs)
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);
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// F[io7_mux]: 15:14
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prim_subreg #(
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.DW (2),
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.SWACCESS("RW"),
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.RESVAL (2'h0)
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) u_ctrl_io7_mux (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_io7_mux_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.ctrl.io7_mux.q),
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// to register interface (read)
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.qs (ctrl_io7_mux_qs)
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);
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// F[io8_mux]: 17:16
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prim_subreg #(
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.DW (2),
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.SWACCESS("RW"),
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.RESVAL (2'h0)
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) u_ctrl_io8_mux (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_io8_mux_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.ctrl.io8_mux.q),
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// to register interface (read)
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.qs (ctrl_io8_mux_qs)
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);
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// F[io9_mux]: 19:18
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prim_subreg #(
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.DW (2),
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.SWACCESS("RW"),
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.RESVAL (2'h0)
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) u_ctrl_io9_mux (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_io9_mux_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.ctrl.io9_mux.q),
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// to register interface (read)
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.qs (ctrl_io9_mux_qs)
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);
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// F[io10_mux]: 21:20
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prim_subreg #(
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.DW (2),
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.SWACCESS("RW"),
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.RESVAL (2'h0)
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) u_ctrl_io10_mux (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_io10_mux_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.ctrl.io10_mux.q),
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// to register interface (read)
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.qs (ctrl_io10_mux_qs)
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);
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// F[io11_mux]: 23:22
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prim_subreg #(
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.DW (2),
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.SWACCESS("RW"),
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.RESVAL (2'h0)
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) u_ctrl_io11_mux (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_io11_mux_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.ctrl.io11_mux.q),
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// to register interface (read)
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.qs (ctrl_io11_mux_qs)
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);
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// F[io12_mux]: 25:24
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prim_subreg #(
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.DW (2),
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.SWACCESS("RW"),
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.RESVAL (2'h0)
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) u_ctrl_io12_mux (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_io12_mux_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.ctrl.io12_mux.q),
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// to register interface (read)
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.qs (ctrl_io12_mux_qs)
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);
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// F[io13_mux]: 27:26
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prim_subreg #(
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.DW (2),
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.SWACCESS("RW"),
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.RESVAL (2'h0)
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) u_ctrl_io13_mux (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_io13_mux_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.ctrl.io13_mux.q),
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// to register interface (read)
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.qs (ctrl_io13_mux_qs)
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);
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// F[io14_mux]: 29:28
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prim_subreg #(
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.DW (2),
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.SWACCESS("RW"),
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.RESVAL (2'h0)
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) u_ctrl_io14_mux (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_io14_mux_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.ctrl.io14_mux.q),
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// to register interface (read)
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.qs (ctrl_io14_mux_qs)
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);
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// F[io15_mux]: 31:30
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prim_subreg #(
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.DW (2),
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.SWACCESS("RW"),
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.RESVAL (2'h0)
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) u_ctrl_io15_mux (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_io15_mux_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.ctrl.io15_mux.q),
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// to register interface (read)
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.qs (ctrl_io15_mux_qs)
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);
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logic [0:0] addr_hit;
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always_comb begin
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addr_hit = '0;
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addr_hit[0] = (reg_addr == PINMUX_CTRL_OFFSET);
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end
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assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
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// Check sub-word write is permitted
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always_comb begin
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wr_err = (reg_we &
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((addr_hit[0] & (|(PINMUX_PERMIT[0] & ~reg_be)))));
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end
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assign ctrl_we = addr_hit[0] & reg_we & !reg_error;
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assign ctrl_io0_mux_wd = reg_wdata[1:0];
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assign ctrl_io1_mux_wd = reg_wdata[3:2];
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assign ctrl_io2_mux_wd = reg_wdata[5:4];
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assign ctrl_io3_mux_wd = reg_wdata[7:6];
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assign ctrl_io4_mux_wd = reg_wdata[9:8];
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assign ctrl_io5_mux_wd = reg_wdata[11:10];
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assign ctrl_io6_mux_wd = reg_wdata[13:12];
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assign ctrl_io7_mux_wd = reg_wdata[15:14];
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assign ctrl_io8_mux_wd = reg_wdata[17:16];
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assign ctrl_io9_mux_wd = reg_wdata[19:18];
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assign ctrl_io10_mux_wd = reg_wdata[21:20];
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assign ctrl_io11_mux_wd = reg_wdata[23:22];
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assign ctrl_io12_mux_wd = reg_wdata[25:24];
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assign ctrl_io13_mux_wd = reg_wdata[27:26];
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assign ctrl_io14_mux_wd = reg_wdata[29:28];
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assign ctrl_io15_mux_wd = reg_wdata[31:30];
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// Read data return
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always_comb begin
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reg_rdata_next = '0;
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unique case (1'b1)
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addr_hit[0]: begin
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reg_rdata_next[1:0] = ctrl_io0_mux_qs;
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reg_rdata_next[3:2] = ctrl_io1_mux_qs;
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reg_rdata_next[5:4] = ctrl_io2_mux_qs;
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reg_rdata_next[7:6] = ctrl_io3_mux_qs;
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reg_rdata_next[9:8] = ctrl_io4_mux_qs;
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reg_rdata_next[11:10] = ctrl_io5_mux_qs;
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reg_rdata_next[13:12] = ctrl_io6_mux_qs;
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reg_rdata_next[15:14] = ctrl_io7_mux_qs;
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reg_rdata_next[17:16] = ctrl_io8_mux_qs;
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reg_rdata_next[19:18] = ctrl_io9_mux_qs;
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reg_rdata_next[21:20] = ctrl_io10_mux_qs;
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reg_rdata_next[23:22] = ctrl_io11_mux_qs;
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reg_rdata_next[25:24] = ctrl_io12_mux_qs;
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reg_rdata_next[27:26] = ctrl_io13_mux_qs;
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reg_rdata_next[29:28] = ctrl_io14_mux_qs;
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reg_rdata_next[31:30] = ctrl_io15_mux_qs;
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end
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default: begin
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reg_rdata_next = '1;
|
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end
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endcase
|
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end
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|
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// Unused signal tieoff
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|
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// wdata / byte enable are not always fully used
|
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// add a blanket unused statement to handle lint waivers
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logic unused_wdata;
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logic unused_be;
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assign unused_wdata = ^reg_wdata;
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assign unused_be = ^reg_be;
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|
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endmodule
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