67 lines
2.0 KiB
Systemverilog
67 lines
2.0 KiB
Systemverilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "../core/defines.sv"
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module ram #(
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parameter DP = 4096
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)(
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input wire clk_i,
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input wire rst_ni,
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input wire req_i,
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input wire we_i,
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input wire [ 3:0] be_i,
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input wire [31:0] addr_i,
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input wire [31:0] data_i,
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output wire gnt_o,
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output wire rvalid_o,
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output wire [31:0] data_o
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);
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reg rvalid_q;
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wire[31:0] addr;
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assign addr = {6'h0, addr_i[27:2]};
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assign gnt_o = req_i;
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always @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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rvalid_q <= 1'b0;
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end else begin
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rvalid_q <= req_i;
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end
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end
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assign rvalid_o = rvalid_q;
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gen_ram #(
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.DP(DP),
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.DW(32),
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.MW(4),
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.AW(32)
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) u_gen_ram(
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.clk(clk_i),
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.addr_i(addr),
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.data_i(data_i),
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.sel_i(be_i),
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.we_i(we_i),
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.data_o(data_o)
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);
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endmodule
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