676 lines
16 KiB
Systemverilog
676 lines
16 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Register Top module auto-generated by `reggen`
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module spi_reg_top (
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input logic clk_i,
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input logic rst_ni,
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// To HW
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output spi_reg_pkg::spi_reg2hw_t reg2hw, // Write
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input spi_reg_pkg::spi_hw2reg_t hw2reg, // Read
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input logic reg_we,
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input logic reg_re,
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input logic [31:0] reg_wdata,
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input logic [ 3:0] reg_be,
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input logic [31:0] reg_addr,
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output logic [31:0] reg_rdata
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);
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import spi_reg_pkg::* ;
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localparam int AW = 4;
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localparam int DW = 32;
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localparam int DBW = DW/8; // Byte Width
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logic reg_error;
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logic addrmiss, wr_err;
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logic [DW-1:0] reg_rdata_next;
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assign reg_rdata = reg_rdata_next;
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assign reg_error = wr_err;
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// Define SW related signals
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// Format: <reg>_<field>_{wd|we|qs}
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// or <reg>_{wd|we|qs} if field == 1 or 0
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logic ctrl0_we;
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logic ctrl0_enable_qs;
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logic ctrl0_enable_wd;
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logic ctrl0_int_en_qs;
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logic ctrl0_int_en_wd;
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logic ctrl0_int_pending_qs;
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logic ctrl0_int_pending_wd;
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logic ctrl0_role_mode_qs;
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logic ctrl0_role_mode_wd;
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logic [1:0] ctrl0_cp_mode_qs;
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logic [1:0] ctrl0_cp_mode_wd;
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logic [1:0] ctrl0_spi_mode_qs;
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logic [1:0] ctrl0_spi_mode_wd;
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logic ctrl0_read_qs;
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logic ctrl0_read_wd;
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logic ctrl0_msb_first_qs;
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logic ctrl0_msb_first_wd;
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logic ctrl0_ss_sw_ctrl_qs;
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logic ctrl0_ss_sw_ctrl_wd;
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logic ctrl0_ss_level_qs;
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logic ctrl0_ss_level_wd;
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logic [3:0] ctrl0_ss_delay_qs;
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logic [3:0] ctrl0_ss_delay_wd;
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logic ctrl0_tx_fifo_reset_qs;
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logic ctrl0_tx_fifo_reset_wd;
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logic ctrl0_rx_fifo_reset_qs;
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logic ctrl0_rx_fifo_reset_wd;
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logic [2:0] ctrl0_clk_div_qs;
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logic [2:0] ctrl0_clk_div_wd;
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logic status_re;
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logic status_tx_fifo_full_qs;
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logic status_tx_fifo_empty_qs;
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logic status_rx_fifo_full_qs;
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logic status_rx_fifo_empty_qs;
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logic status_busy_qs;
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logic txdata_we;
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logic [31:0] txdata_wd;
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logic rxdata_re;
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logic [31:0] rxdata_qs;
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// Register instances
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// R[ctrl0]: V(False)
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// F[enable]: 0:0
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prim_subreg #(
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.DW (1),
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.SWACCESS("RW"),
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.RESVAL (1'h0)
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) u_ctrl0_enable (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl0_we),
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.wd (ctrl0_enable_wd),
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// from internal hardware
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.de (hw2reg.ctrl0.enable.de),
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.d (hw2reg.ctrl0.enable.d),
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// to internal hardware
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.qe (reg2hw.ctrl0.enable.qe),
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.q (reg2hw.ctrl0.enable.q),
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// to register interface (read)
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.qs (ctrl0_enable_qs)
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);
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// F[int_en]: 1:1
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prim_subreg #(
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.DW (1),
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.SWACCESS("RW"),
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.RESVAL (1'h0)
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) u_ctrl0_int_en (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl0_we),
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.wd (ctrl0_int_en_wd),
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// from internal hardware
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.de (hw2reg.ctrl0.int_en.de),
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.d (hw2reg.ctrl0.int_en.d),
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// to internal hardware
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.qe (reg2hw.ctrl0.int_en.qe),
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.q (reg2hw.ctrl0.int_en.q),
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// to register interface (read)
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.qs (ctrl0_int_en_qs)
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);
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// F[int_pending]: 2:2
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prim_subreg #(
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.DW (1),
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.SWACCESS("W1C"),
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.RESVAL (1'h0)
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) u_ctrl0_int_pending (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl0_we),
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.wd (ctrl0_int_pending_wd),
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// from internal hardware
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.de (hw2reg.ctrl0.int_pending.de),
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.d (hw2reg.ctrl0.int_pending.d),
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// to internal hardware
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.qe (reg2hw.ctrl0.int_pending.qe),
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.q (reg2hw.ctrl0.int_pending.q),
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// to register interface (read)
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.qs (ctrl0_int_pending_qs)
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);
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// F[role_mode]: 3:3
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prim_subreg #(
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.DW (1),
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.SWACCESS("RW"),
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.RESVAL (1'h0)
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) u_ctrl0_role_mode (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl0_we),
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.wd (ctrl0_role_mode_wd),
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// from internal hardware
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.de (hw2reg.ctrl0.role_mode.de),
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.d (hw2reg.ctrl0.role_mode.d),
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// to internal hardware
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.qe (reg2hw.ctrl0.role_mode.qe),
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.q (reg2hw.ctrl0.role_mode.q),
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// to register interface (read)
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.qs (ctrl0_role_mode_qs)
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);
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// F[cp_mode]: 5:4
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prim_subreg #(
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.DW (2),
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.SWACCESS("RW"),
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.RESVAL (2'h0)
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) u_ctrl0_cp_mode (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl0_we),
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.wd (ctrl0_cp_mode_wd),
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// from internal hardware
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.de (hw2reg.ctrl0.cp_mode.de),
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.d (hw2reg.ctrl0.cp_mode.d),
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// to internal hardware
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.qe (reg2hw.ctrl0.cp_mode.qe),
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.q (reg2hw.ctrl0.cp_mode.q),
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// to register interface (read)
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.qs (ctrl0_cp_mode_qs)
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);
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// F[spi_mode]: 7:6
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prim_subreg #(
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.DW (2),
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.SWACCESS("RW"),
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.RESVAL (2'h0)
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) u_ctrl0_spi_mode (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl0_we),
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.wd (ctrl0_spi_mode_wd),
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// from internal hardware
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.de (hw2reg.ctrl0.spi_mode.de),
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.d (hw2reg.ctrl0.spi_mode.d),
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// to internal hardware
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.qe (reg2hw.ctrl0.spi_mode.qe),
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.q (reg2hw.ctrl0.spi_mode.q),
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// to register interface (read)
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.qs (ctrl0_spi_mode_qs)
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);
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// F[read]: 8:8
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prim_subreg #(
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.DW (1),
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.SWACCESS("RW"),
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.RESVAL (1'h0)
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) u_ctrl0_read (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl0_we),
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.wd (ctrl0_read_wd),
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// from internal hardware
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.de (hw2reg.ctrl0.read.de),
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.d (hw2reg.ctrl0.read.d),
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// to internal hardware
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.qe (reg2hw.ctrl0.read.qe),
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.q (reg2hw.ctrl0.read.q),
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// to register interface (read)
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.qs (ctrl0_read_qs)
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);
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// F[msb_first]: 9:9
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prim_subreg #(
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.DW (1),
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.SWACCESS("RW"),
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.RESVAL (1'h0)
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) u_ctrl0_msb_first (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl0_we),
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.wd (ctrl0_msb_first_wd),
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// from internal hardware
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.de (hw2reg.ctrl0.msb_first.de),
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.d (hw2reg.ctrl0.msb_first.d),
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// to internal hardware
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.qe (reg2hw.ctrl0.msb_first.qe),
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.q (reg2hw.ctrl0.msb_first.q),
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// to register interface (read)
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.qs (ctrl0_msb_first_qs)
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);
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// F[ss_sw_ctrl]: 10:10
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prim_subreg #(
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.DW (1),
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.SWACCESS("RW"),
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.RESVAL (1'h0)
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) u_ctrl0_ss_sw_ctrl (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl0_we),
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.wd (ctrl0_ss_sw_ctrl_wd),
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// from internal hardware
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.de (hw2reg.ctrl0.ss_sw_ctrl.de),
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.d (hw2reg.ctrl0.ss_sw_ctrl.d),
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// to internal hardware
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.qe (reg2hw.ctrl0.ss_sw_ctrl.qe),
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.q (reg2hw.ctrl0.ss_sw_ctrl.q),
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// to register interface (read)
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.qs (ctrl0_ss_sw_ctrl_qs)
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);
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// F[ss_level]: 11:11
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prim_subreg #(
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.DW (1),
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.SWACCESS("RW"),
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.RESVAL (1'h0)
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) u_ctrl0_ss_level (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl0_we),
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.wd (ctrl0_ss_level_wd),
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// from internal hardware
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.de (hw2reg.ctrl0.ss_level.de),
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.d (hw2reg.ctrl0.ss_level.d),
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// to internal hardware
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.qe (reg2hw.ctrl0.ss_level.qe),
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.q (reg2hw.ctrl0.ss_level.q),
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// to register interface (read)
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.qs (ctrl0_ss_level_qs)
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);
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// F[ss_delay]: 15:12
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prim_subreg #(
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.DW (4),
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.SWACCESS("RW"),
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.RESVAL (4'h0)
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) u_ctrl0_ss_delay (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl0_we),
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.wd (ctrl0_ss_delay_wd),
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// from internal hardware
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.de (hw2reg.ctrl0.ss_delay.de),
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.d (hw2reg.ctrl0.ss_delay.d),
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// to internal hardware
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.qe (reg2hw.ctrl0.ss_delay.qe),
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.q (reg2hw.ctrl0.ss_delay.q),
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// to register interface (read)
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.qs (ctrl0_ss_delay_qs)
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);
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// F[tx_fifo_reset]: 16:16
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prim_subreg #(
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.DW (1),
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.SWACCESS("W1C"),
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.RESVAL (1'h0)
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) u_ctrl0_tx_fifo_reset (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl0_we),
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.wd (ctrl0_tx_fifo_reset_wd),
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// from internal hardware
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.de (hw2reg.ctrl0.tx_fifo_reset.de),
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.d (hw2reg.ctrl0.tx_fifo_reset.d),
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// to internal hardware
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.qe (reg2hw.ctrl0.tx_fifo_reset.qe),
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.q (reg2hw.ctrl0.tx_fifo_reset.q),
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// to register interface (read)
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.qs (ctrl0_tx_fifo_reset_qs)
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);
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// F[rx_fifo_reset]: 17:17
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prim_subreg #(
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.DW (1),
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.SWACCESS("W1C"),
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.RESVAL (1'h0)
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) u_ctrl0_rx_fifo_reset (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl0_we),
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.wd (ctrl0_rx_fifo_reset_wd),
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// from internal hardware
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.de (hw2reg.ctrl0.rx_fifo_reset.de),
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.d (hw2reg.ctrl0.rx_fifo_reset.d),
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// to internal hardware
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.qe (reg2hw.ctrl0.rx_fifo_reset.qe),
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.q (reg2hw.ctrl0.rx_fifo_reset.q),
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// to register interface (read)
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.qs (ctrl0_rx_fifo_reset_qs)
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);
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// F[clk_div]: 31:29
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prim_subreg #(
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.DW (3),
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.SWACCESS("RW"),
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.RESVAL (3'h0)
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) u_ctrl0_clk_div (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl0_we),
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.wd (ctrl0_clk_div_wd),
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// from internal hardware
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.de (hw2reg.ctrl0.clk_div.de),
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.d (hw2reg.ctrl0.clk_div.d),
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// to internal hardware
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.qe (reg2hw.ctrl0.clk_div.qe),
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.q (reg2hw.ctrl0.clk_div.q),
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// to register interface (read)
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.qs (ctrl0_clk_div_qs)
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);
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// R[status]: V(True)
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// F[tx_fifo_full]: 0:0
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prim_subreg_ext #(
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.DW (1)
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) u_status_tx_fifo_full (
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.re (status_re),
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.we (1'b0),
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.wd ('0),
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.d (hw2reg.status.tx_fifo_full.d),
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.qre (),
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.qe (),
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.q (reg2hw.status.tx_fifo_full.q),
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.qs (status_tx_fifo_full_qs)
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);
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// F[tx_fifo_empty]: 1:1
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prim_subreg_ext #(
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.DW (1)
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) u_status_tx_fifo_empty (
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.re (status_re),
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.we (1'b0),
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.wd ('0),
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.d (hw2reg.status.tx_fifo_empty.d),
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.qre (),
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.qe (),
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.q (reg2hw.status.tx_fifo_empty.q),
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.qs (status_tx_fifo_empty_qs)
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);
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// F[rx_fifo_full]: 2:2
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prim_subreg_ext #(
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.DW (1)
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) u_status_rx_fifo_full (
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.re (status_re),
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.we (1'b0),
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.wd ('0),
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.d (hw2reg.status.rx_fifo_full.d),
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.qre (),
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.qe (),
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.q (reg2hw.status.rx_fifo_full.q),
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.qs (status_rx_fifo_full_qs)
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);
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// F[rx_fifo_empty]: 3:3
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prim_subreg_ext #(
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.DW (1)
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) u_status_rx_fifo_empty (
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.re (status_re),
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.we (1'b0),
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.wd ('0),
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.d (hw2reg.status.rx_fifo_empty.d),
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.qre (),
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.qe (),
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.q (reg2hw.status.rx_fifo_empty.q),
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.qs (status_rx_fifo_empty_qs)
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);
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// F[busy]: 4:4
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prim_subreg_ext #(
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.DW (1)
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) u_status_busy (
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.re (status_re),
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.we (1'b0),
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.wd ('0),
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.d (hw2reg.status.busy.d),
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.qre (),
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.qe (),
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.q (reg2hw.status.busy.q),
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.qs (status_busy_qs)
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);
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// R[txdata]: V(False)
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prim_subreg #(
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.DW (32),
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.SWACCESS("WO"),
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.RESVAL (32'h0)
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) u_txdata (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (txdata_we),
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.wd (txdata_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (reg2hw.txdata.qe),
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.q (reg2hw.txdata.q),
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|
|
|
// to register interface (read)
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|
.qs ()
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|
);
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|
|
|
|
|
// R[rxdata]: V(True)
|
|
|
|
prim_subreg_ext #(
|
|
.DW (32)
|
|
) u_rxdata (
|
|
.re (rxdata_re),
|
|
.we (1'b0),
|
|
.wd ('0),
|
|
.d (hw2reg.rxdata.d),
|
|
.qre (reg2hw.rxdata.re),
|
|
.qe (),
|
|
.q (reg2hw.rxdata.q),
|
|
.qs (rxdata_qs)
|
|
);
|
|
|
|
|
|
logic [3:0] addr_hit;
|
|
always_comb begin
|
|
addr_hit = '0;
|
|
addr_hit[0] = (reg_addr == SPI_CTRL0_OFFSET);
|
|
addr_hit[1] = (reg_addr == SPI_STATUS_OFFSET);
|
|
addr_hit[2] = (reg_addr == SPI_TXDATA_OFFSET);
|
|
addr_hit[3] = (reg_addr == SPI_RXDATA_OFFSET);
|
|
end
|
|
|
|
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
|
|
|
|
// Check sub-word write is permitted
|
|
always_comb begin
|
|
wr_err = (reg_we &
|
|
((addr_hit[0] & (|(SPI_PERMIT[0] & ~reg_be))) |
|
|
(addr_hit[1] & (|(SPI_PERMIT[1] & ~reg_be))) |
|
|
(addr_hit[2] & (|(SPI_PERMIT[2] & ~reg_be))) |
|
|
(addr_hit[3] & (|(SPI_PERMIT[3] & ~reg_be)))));
|
|
end
|
|
|
|
assign ctrl0_we = addr_hit[0] & reg_we & !reg_error;
|
|
|
|
assign ctrl0_enable_wd = reg_wdata[0];
|
|
|
|
assign ctrl0_int_en_wd = reg_wdata[1];
|
|
|
|
assign ctrl0_int_pending_wd = reg_wdata[2];
|
|
|
|
assign ctrl0_role_mode_wd = reg_wdata[3];
|
|
|
|
assign ctrl0_cp_mode_wd = reg_wdata[5:4];
|
|
|
|
assign ctrl0_spi_mode_wd = reg_wdata[7:6];
|
|
|
|
assign ctrl0_read_wd = reg_wdata[8];
|
|
|
|
assign ctrl0_msb_first_wd = reg_wdata[9];
|
|
|
|
assign ctrl0_ss_sw_ctrl_wd = reg_wdata[10];
|
|
|
|
assign ctrl0_ss_level_wd = reg_wdata[11];
|
|
|
|
assign ctrl0_ss_delay_wd = reg_wdata[15:12];
|
|
|
|
assign ctrl0_tx_fifo_reset_wd = reg_wdata[16];
|
|
|
|
assign ctrl0_rx_fifo_reset_wd = reg_wdata[17];
|
|
|
|
assign ctrl0_clk_div_wd = reg_wdata[31:29];
|
|
assign status_re = addr_hit[1] & reg_re & !reg_error;
|
|
assign txdata_we = addr_hit[2] & reg_we & !reg_error;
|
|
|
|
assign txdata_wd = reg_wdata[31:0];
|
|
assign rxdata_re = addr_hit[3] & reg_re & !reg_error;
|
|
|
|
// Read data return
|
|
always_comb begin
|
|
reg_rdata_next = '0;
|
|
unique case (1'b1)
|
|
addr_hit[0]: begin
|
|
reg_rdata_next[0] = ctrl0_enable_qs;
|
|
reg_rdata_next[1] = ctrl0_int_en_qs;
|
|
reg_rdata_next[2] = ctrl0_int_pending_qs;
|
|
reg_rdata_next[3] = ctrl0_role_mode_qs;
|
|
reg_rdata_next[5:4] = ctrl0_cp_mode_qs;
|
|
reg_rdata_next[7:6] = ctrl0_spi_mode_qs;
|
|
reg_rdata_next[8] = ctrl0_read_qs;
|
|
reg_rdata_next[9] = ctrl0_msb_first_qs;
|
|
reg_rdata_next[10] = ctrl0_ss_sw_ctrl_qs;
|
|
reg_rdata_next[11] = ctrl0_ss_level_qs;
|
|
reg_rdata_next[15:12] = ctrl0_ss_delay_qs;
|
|
reg_rdata_next[16] = ctrl0_tx_fifo_reset_qs;
|
|
reg_rdata_next[17] = ctrl0_rx_fifo_reset_qs;
|
|
reg_rdata_next[31:29] = ctrl0_clk_div_qs;
|
|
end
|
|
|
|
addr_hit[1]: begin
|
|
reg_rdata_next[0] = status_tx_fifo_full_qs;
|
|
reg_rdata_next[1] = status_tx_fifo_empty_qs;
|
|
reg_rdata_next[2] = status_rx_fifo_full_qs;
|
|
reg_rdata_next[3] = status_rx_fifo_empty_qs;
|
|
reg_rdata_next[4] = status_busy_qs;
|
|
end
|
|
|
|
addr_hit[2]: begin
|
|
reg_rdata_next[31:0] = '0;
|
|
end
|
|
|
|
addr_hit[3]: begin
|
|
reg_rdata_next[31:0] = rxdata_qs;
|
|
end
|
|
|
|
default: begin
|
|
reg_rdata_next = '1;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
// Unused signal tieoff
|
|
|
|
// wdata / byte enable are not always fully used
|
|
// add a blanket unused statement to handle lint waivers
|
|
logic unused_wdata;
|
|
logic unused_be;
|
|
assign unused_wdata = ^reg_wdata;
|
|
assign unused_be = ^reg_be;
|
|
|
|
endmodule
|