63 lines
2.0 KiB
C
63 lines
2.0 KiB
C
// Generated register defines for timer
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// Copyright information found in source file:
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// Copyright lowRISC contributors.
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// Licensing information found in source file:
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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#ifndef _TIMER_REG_DEFS_
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#define _TIMER_REG_DEFS_
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Register width
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#define TIMER_PARAM_REG_WIDTH 32
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#define TIMER0_BASE_ADDR (0x04000000)
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#define TIMER1_BASE_ADDR (0x0C000000)
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#define TIMER2_BASE_ADDR (0x0D000000)
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#define TIMER0 (TIMER0_BASE_ADDR)
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#define TIMER1 (TIMER1_BASE_ADDR)
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#define TIMER2 (TIMER2_BASE_ADDR)
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#define TIMER_REG(base, offset) (*((volatile uint32_t *)(base + offset)))
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void timer_start(uint32_t base, uint8_t en);
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void timer_set_value(uint32_t base, uint32_t val);
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void timer_set_int_enable(uint32_t base, uint8_t en);
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void timer_clear_int_pending(uint32_t base);
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uint8_t timer_get_int_pending(uint32_t base);
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uint32_t timer_get_current_count(uint32_t base);
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void timer_set_mode_auto_reload(uint32_t base);
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void timer_set_mode_ontshot(uint32_t base);
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void timer_set_clk_div(uint32_t base, uint32_t div);
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// Timer control register
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#define TIMER_CTRL_REG_OFFSET 0x0
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#define TIMER_CTRL_REG_RESVAL 0x0
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#define TIMER_CTRL_EN_BIT 0
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#define TIMER_CTRL_INT_EN_BIT 1
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#define TIMER_CTRL_INT_PENDING_BIT 2
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#define TIMER_CTRL_MODE_BIT 3
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#define TIMER_CTRL_CLK_DIV_MASK 0xffffff
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#define TIMER_CTRL_CLK_DIV_OFFSET 8
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#define TIMER_CTRL_CLK_DIV_FIELD \
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((bitfield_field32_t) { .mask = TIMER_CTRL_CLK_DIV_MASK, .index = TIMER_CTRL_CLK_DIV_OFFSET })
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// Timer expired value register
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#define TIMER_VALUE_REG_OFFSET 0x4
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#define TIMER_VALUE_REG_RESVAL 0x0
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// Timer current count register
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#define TIMER_COUNT_REG_OFFSET 0x8
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#define TIMER_COUNT_REG_RESVAL 0x0
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif // _TIMER_REG_DEFS_
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// End generated register defines for timer
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