332 lines
10 KiB
Verilog
332 lines
10 KiB
Verilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// 串口模块(默认: 115200, 8 N 1)
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module uart(
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input wire clk,
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input wire rst,
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input wire we_i,
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input wire req_i,
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input wire[31:0] addr_i,
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input wire[31:0] data_i,
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output reg[31:0] data_o,
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output reg ack_o,
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output wire tx_pin,
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input wire rx_pin
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);
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// 50MHz时钟，波特率115200bps对应的分频系数
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localparam BAUD_115200 = 32'h1B8;
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localparam S_IDLE = 4'b0001;
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localparam S_START = 4'b0010;
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localparam S_SEND_BYTE = 4'b0100;
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localparam S_STOP = 4'b1000;
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reg tx_data_valid;
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reg tx_data_ready;
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reg[3:0] state;
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reg[15:0] cycle_cnt;
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reg[3:0] bit_cnt;
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reg[7:0] tx_data;
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reg tx_reg;
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reg rx_q0;
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reg rx_q1;
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wire rx_negedge;
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reg rx_start; // RX使能
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reg[3:0] rx_clk_edge_cnt; // clk时钟沿的个数
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reg rx_clk_edge_level; // clk沿电平
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reg rx_done;
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reg[15:0] rx_clk_cnt;
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reg[15:0] rx_div_cnt;
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reg[7:0] rx_data;
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reg rx_over;
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localparam UART_CTRL = 8'h0;
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localparam UART_STATUS = 8'h4;
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localparam UART_BAUD = 8'h8;
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localparam UART_TXDATA = 8'hc;
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localparam UART_RXDATA = 8'h10;
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// addr: 0x00
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// rw. bit[0]: tx enable, 1 = enable, 0 = disable
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// rw. bit[1]: rx enable, 1 = enable, 0 = disable
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reg[31:0] uart_ctrl;
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// addr: 0x04
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// ro. bit[0]: tx busy, 1 = busy, 0 = idle
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// rw. bit[1]: rx over, 1 = over, 0 = receiving
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// must check this bit before tx data
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reg[31:0] uart_status;
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// addr: 0x08
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// rw. clk div
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reg[31:0] uart_baud;
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// addr: 0x10
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// ro. rx data
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reg[31:0] uart_rx;
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assign tx_pin = tx_reg;
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// 写寄存器
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always @ (posedge clk) begin
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if (rst == 1'b0) begin
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uart_ctrl <= 32'h0;
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uart_status <= 32'h0;
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uart_rx <= 32'h0;
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uart_baud <= BAUD_115200;
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tx_data_valid <= 1'b0;
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end else begin
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if (we_i == 1'b1) begin
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case (addr_i[7:0])
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UART_CTRL: begin
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uart_ctrl <= data_i;
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end
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UART_BAUD: begin
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uart_baud <= data_i;
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end
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UART_STATUS: begin
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uart_status[1] <= data_i[1];
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end
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UART_TXDATA: begin
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if (uart_ctrl[0] == 1'b1 && uart_status[0] == 1'b0) begin
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tx_data <= data_i[7:0];
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uart_status[0] <= 1'b1;
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tx_data_valid <= 1'b1;
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end
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end
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endcase
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end else begin
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tx_data_valid <= 1'b0;
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if (tx_data_ready == 1'b1) begin
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uart_status[0] <= 1'b0;
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end
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if (uart_ctrl[1] == 1'b1) begin
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if (rx_over == 1'b1) begin
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uart_status[1] <= 1'b1;
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uart_rx <= {24'h0, rx_data};
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end
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end
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end
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end
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end
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// 读寄存器
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always @ (*) begin
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if (rst == 1'b0) begin
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data_o = 32'h0;
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end else begin
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case (addr_i[7:0])
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UART_CTRL: begin
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data_o = uart_ctrl;
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end
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UART_STATUS: begin
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data_o = uart_status;
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end
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UART_BAUD: begin
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data_o = uart_baud;
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end
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UART_RXDATA: begin
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data_o = uart_rx;
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end
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default: begin
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data_o = 32'h0;
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end
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endcase
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end
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end
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// *************************** TX发送 ****************************
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always @ (posedge clk) begin
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if (rst == 1'b0) begin
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state <= S_IDLE;
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cycle_cnt <= 16'd0;
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tx_reg <= 1'b0;
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bit_cnt <= 4'd0;
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tx_data_ready <= 1'b0;
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end else begin
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if (state == S_IDLE) begin
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tx_reg <= 1'b1;
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tx_data_ready <= 1'b0;
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if (tx_data_valid == 1'b1) begin
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state <= S_START;
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cycle_cnt <= 16'd0;
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bit_cnt <= 4'd0;
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tx_reg <= 1'b0;
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end
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end else begin
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cycle_cnt <= cycle_cnt + 16'd1;
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if (cycle_cnt == uart_baud[15:0]) begin
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cycle_cnt <= 16'd0;
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case (state)
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S_START: begin
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tx_reg <= tx_data[bit_cnt];
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state <= S_SEND_BYTE;
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bit_cnt <= bit_cnt + 4'd1;
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end
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S_SEND_BYTE: begin
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bit_cnt <= bit_cnt + 4'd1;
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if (bit_cnt == 4'd8) begin
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state <= S_STOP;
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tx_reg <= 1'b1;
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end else begin
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tx_reg <= tx_data[bit_cnt];
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end
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end
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S_STOP: begin
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tx_reg <= 1'b1;
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state <= S_IDLE;
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tx_data_ready <= 1'b1;
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end
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endcase
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end
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end
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end
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end
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// *************************** RX接收 ****************************
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// 下降沿检测(检测起始信号)
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assign rx_negedge = rx_q1 && ~rx_q0;
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always @ (posedge clk) begin
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if (rst == 1'b0) begin
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rx_q0 <= 1'b0;
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rx_q1 <= 1'b0;
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end else begin
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rx_q0 <= rx_pin;
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rx_q1 <= rx_q0;
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end
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end
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// 开始接收数据信号，接收期间一直有效
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always @ (posedge clk) begin
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if (rst == 1'b0) begin
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rx_start <= 1'b0;
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end else begin
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if (uart_ctrl[1]) begin
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if (rx_negedge) begin
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rx_start <= 1'b1;
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end else if (rx_clk_edge_cnt == 4'd9) begin
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rx_start <= 1'b0;
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end
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end else begin
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rx_start <= 1'b0;
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end
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end
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end
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always @ (posedge clk) begin
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if (rst == 1'b0) begin
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rx_div_cnt <= 16'h0;
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end else begin
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// 第一个时钟沿只需波特率分频系数的一半
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if (rx_start == 1'b1 && rx_clk_edge_cnt == 4'h0) begin
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rx_div_cnt <= {1'b0, uart_baud[15:1]};
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end else begin
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rx_div_cnt <= uart_baud[15:0];
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end
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end
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end
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// 对时钟进行计数
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always @ (posedge clk) begin
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if (rst == 1'b0) begin
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rx_clk_cnt <= 16'h0;
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end else if (rx_start == 1'b1) begin
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// 计数达到分频值
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if (rx_clk_cnt == rx_div_cnt) begin
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rx_clk_cnt <= 16'h0;
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end else begin
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rx_clk_cnt <= rx_clk_cnt + 1'b1;
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end
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end else begin
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rx_clk_cnt <= 16'h0;
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end
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end
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// 每当时钟计数达到分频值时产生一个上升沿脉冲
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always @ (posedge clk) begin
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if (rst == 1'b0) begin
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rx_clk_edge_cnt <= 4'h0;
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rx_clk_edge_level <= 1'b0;
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end else if (rx_start == 1'b1) begin
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// 计数达到分频值
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if (rx_clk_cnt == rx_div_cnt) begin
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// 时钟沿个数达到最大值
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if (rx_clk_edge_cnt == 4'd9) begin
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rx_clk_edge_cnt <= 4'h0;
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rx_clk_edge_level <= 1'b0;
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end else begin
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// 时钟沿个数加1
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rx_clk_edge_cnt <= rx_clk_edge_cnt + 1'b1;
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// 产生上升沿脉冲
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rx_clk_edge_level <= 1'b1;
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end
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end else begin
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rx_clk_edge_level <= 1'b0;
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end
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end else begin
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rx_clk_edge_cnt <= 4'h0;
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rx_clk_edge_level <= 1'b0;
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end
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end
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// bit序列
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always @ (posedge clk) begin
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if (rst == 1'b0) begin
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rx_data <= 8'h0;
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rx_over <= 1'b0;
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end else begin
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if (rx_start == 1'b1) begin
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// 上升沿
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if (rx_clk_edge_level == 1'b1) begin
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case (rx_clk_edge_cnt)
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// 起始位
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1: begin
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end
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// 数据位
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2, 3, 4, 5, 6, 7, 8, 9: begin
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rx_data <= rx_data | (rx_pin << (rx_clk_edge_cnt - 2));
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// 最后一位接收完成，置位接收完成标志
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if (rx_clk_edge_cnt == 4'h9) begin
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rx_over <= 1'b1;
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end
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end
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endcase
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end
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end else begin
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rx_data <= 8'h0;
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rx_over <= 1'b0;
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end
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end
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end
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endmodule
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