tinyriscv/fpga/xilinx/cmod_a7
liangkangnan 4c16dfb254 rtl: move top module into fpga dir
Signed-off-by: liangkangnan <liangkangnan@163.com>
2022-08-10 08:13:38 +08:00
..
constrs rtl: move top module into fpga dir 2022-08-10 08:13:38 +08:00
scripts rtl: move top module into fpga dir 2022-08-10 08:13:38 +08:00
.gitignore rtl: move top module into fpga dir 2022-08-10 08:13:38 +08:00
Makefile rtl: move top module into fpga dir 2022-08-10 08:13:38 +08:00
tinyriscv_soc_top.sv rtl: move top module into fpga dir 2022-08-10 08:13:38 +08:00