122 lines
3.5 KiB
Systemverilog
122 lines
3.5 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Register Package auto-generated by `reggen` containing data structure
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package rvic_reg_pkg;
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// Address widths within the block
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parameter int BlockAw = 6;
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////////////////////////////
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// Typedefs for registers //
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////////////////////////////
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typedef struct packed {
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logic [31:0] q;
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} rvic_reg2hw_enable_reg_t;
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typedef struct packed {
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logic [31:0] q;
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} rvic_reg2hw_pending_reg_t;
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typedef struct packed {
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logic [31:0] q;
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} rvic_reg2hw_priority0_reg_t;
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typedef struct packed {
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logic [31:0] q;
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} rvic_reg2hw_priority1_reg_t;
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typedef struct packed {
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logic [31:0] q;
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} rvic_reg2hw_priority2_reg_t;
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typedef struct packed {
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logic [31:0] q;
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} rvic_reg2hw_priority3_reg_t;
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typedef struct packed {
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logic [31:0] q;
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} rvic_reg2hw_priority4_reg_t;
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typedef struct packed {
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logic [31:0] q;
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} rvic_reg2hw_priority5_reg_t;
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typedef struct packed {
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logic [31:0] q;
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} rvic_reg2hw_priority6_reg_t;
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typedef struct packed {
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logic [31:0] q;
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} rvic_reg2hw_priority7_reg_t;
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typedef struct packed {
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logic [31:0] d;
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logic de;
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} rvic_hw2reg_pending_reg_t;
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// Register -> HW type
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typedef struct packed {
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rvic_reg2hw_enable_reg_t enable; // [319:288]
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rvic_reg2hw_pending_reg_t pending; // [287:256]
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rvic_reg2hw_priority0_reg_t priority0; // [255:224]
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rvic_reg2hw_priority1_reg_t priority1; // [223:192]
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rvic_reg2hw_priority2_reg_t priority2; // [191:160]
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rvic_reg2hw_priority3_reg_t priority3; // [159:128]
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rvic_reg2hw_priority4_reg_t priority4; // [127:96]
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rvic_reg2hw_priority5_reg_t priority5; // [95:64]
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rvic_reg2hw_priority6_reg_t priority6; // [63:32]
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rvic_reg2hw_priority7_reg_t priority7; // [31:0]
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} rvic_reg2hw_t;
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// HW -> register type
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typedef struct packed {
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rvic_hw2reg_pending_reg_t pending; // [32:0]
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} rvic_hw2reg_t;
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// Register offsets
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parameter logic [BlockAw-1:0] RVIC_ENABLE_OFFSET = 6'h0;
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parameter logic [BlockAw-1:0] RVIC_PENDING_OFFSET = 6'h4;
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parameter logic [BlockAw-1:0] RVIC_PRIORITY0_OFFSET = 6'h8;
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parameter logic [BlockAw-1:0] RVIC_PRIORITY1_OFFSET = 6'hc;
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parameter logic [BlockAw-1:0] RVIC_PRIORITY2_OFFSET = 6'h10;
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parameter logic [BlockAw-1:0] RVIC_PRIORITY3_OFFSET = 6'h14;
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parameter logic [BlockAw-1:0] RVIC_PRIORITY4_OFFSET = 6'h18;
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parameter logic [BlockAw-1:0] RVIC_PRIORITY5_OFFSET = 6'h1c;
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parameter logic [BlockAw-1:0] RVIC_PRIORITY6_OFFSET = 6'h20;
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parameter logic [BlockAw-1:0] RVIC_PRIORITY7_OFFSET = 6'h24;
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// Register index
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typedef enum int {
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RVIC_ENABLE,
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RVIC_PENDING,
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RVIC_PRIORITY0,
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RVIC_PRIORITY1,
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RVIC_PRIORITY2,
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RVIC_PRIORITY3,
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RVIC_PRIORITY4,
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RVIC_PRIORITY5,
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RVIC_PRIORITY6,
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RVIC_PRIORITY7
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} rvic_id_e;
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// Register width information to check illegal writes
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parameter logic [3:0] RVIC_PERMIT [10] = '{
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4'b1111, // index[0] RVIC_ENABLE
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4'b1111, // index[1] RVIC_PENDING
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4'b1111, // index[2] RVIC_PRIORITY0
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4'b1111, // index[3] RVIC_PRIORITY1
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4'b1111, // index[4] RVIC_PRIORITY2
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4'b1111, // index[5] RVIC_PRIORITY3
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4'b1111, // index[6] RVIC_PRIORITY4
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4'b1111, // index[7] RVIC_PRIORITY5
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4'b1111, // index[8] RVIC_PRIORITY6
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4'b1111 // index[9] RVIC_PRIORITY7
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};
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endpackage
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