137 lines
4.1 KiB
Verilog
137 lines
4.1 KiB
Verilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// GPIO模块
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module gpio(
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input wire clk,
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input wire rst_n,
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input wire[31:0] addr_i,
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input wire[31:0] data_i,
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input wire[3:0] sel_i,
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input wire we_i,
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output wire[31:0] data_o,
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input wire req_valid_i,
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output wire req_ready_o,
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output wire rsp_valid_o,
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input wire rsp_ready_i,
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input wire[1:0] io_pin_i,
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output wire[31:0] reg_ctrl,
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output wire[31:0] reg_data
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);
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// GPIO寄存器(偏移)地址
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localparam GPIO_CTRL = 4'h0;
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localparam GPIO_DATA = 4'h4;
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// GPIO控制寄存器
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// 每2位控制1个IO的输入、输出模式，最多支持16个IO
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// 0: 高阻，1：输出，2：输入
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reg[31:0] gpio_ctrl;
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// GPIO输入输出数据寄存器
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reg[31:0] gpio_data;
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assign reg_ctrl = gpio_ctrl;
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assign reg_data = gpio_data;
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wire wen = we_i & req_valid_i;
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wire ren = (~we_i) & req_valid_i;
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wire write_reg_ctrl_en = wen & (addr_i[3:0] == GPIO_CTRL);
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wire write_reg_data_en = wen & (addr_i[3:0] == GPIO_DATA);
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// 写gpio_ctrl
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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gpio_ctrl <= 32'h0;
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end else begin
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if (write_reg_ctrl_en) begin
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if (sel_i[0]) begin
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gpio_ctrl[7:0] <= data_i[7:0];
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end
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if (sel_i[1]) begin
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gpio_ctrl[15:8] <= data_i[15:8];
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end
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if (sel_i[2]) begin
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gpio_ctrl[23:16] <= data_i[23:16];
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end
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if (sel_i[3]) begin
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gpio_ctrl[31:24] <= data_i[31:24];
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end
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end
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end
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end
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// 写gpio_data
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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gpio_data <= 32'h0;
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end else begin
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if (write_reg_data_en) begin
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if (sel_i[0]) begin
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gpio_data[7:0] <= data_i[7:0];
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end
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if (sel_i[1]) begin
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gpio_data[15:8] <= data_i[15:8];
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end
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end else begin
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if (gpio_ctrl[1:0] == 2'b10) begin
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gpio_data[0] <= io_pin_i[0];
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end
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if (gpio_ctrl[3:2] == 2'b10) begin
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gpio_data[1] <= io_pin_i[1];
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end
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end
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end
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end
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reg[31:0] data_r;
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// 读寄存器
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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data_r <= 32'h0;
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end else begin
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if (ren) begin
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case (addr_i[3:0])
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GPIO_CTRL: data_r <= gpio_ctrl;
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GPIO_DATA: data_r <= gpio_data;
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default: data_r <= 32'h0;
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endcase
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end else begin
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data_r <= 32'h0;
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end
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end
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end
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assign data_o = data_r;
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vld_rdy #(
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.CUT_READY(0)
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) u_vld_rdy(
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.clk(clk),
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.rst_n(rst_n),
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.vld_i(req_valid_i),
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.rdy_o(req_ready_o),
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.rdy_i(rsp_ready_i),
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.vld_o(rsp_valid_o)
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);
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endmodule
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