435 lines
11 KiB
Verilog
435 lines
11 KiB
Verilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "../core/defines.v"
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// tinyriscv soc顶层模块
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module tinyriscv_soc_top(
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input wire clk,
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input wire rst_ext_i,
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output wire halted_ind, // jtag是否已经halt住CPU信号
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output wire uart_tx_pin, // UART发送引脚
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input wire uart_rx_pin, // UART接收引脚
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inout wire[1:0] gpio, // GPIO引脚
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input wire jtag_TCK, // JTAG TCK引脚
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input wire jtag_TMS, // JTAG TMS引脚
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input wire jtag_TDI, // JTAG TDI引脚
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output wire jtag_TDO // JTAG TDO引脚
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);
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// master 0 interface
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wire[31:0] m0_addr_i;
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wire[31:0] m0_data_i;
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wire[3:0] m0_sel_i;
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wire m0_req_vld_i;
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wire m0_rsp_rdy_i;
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wire m0_we_i;
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wire m0_req_rdy_o;
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wire m0_rsp_vld_o;
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wire[31:0] m0_data_o;
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// master 1 interface
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wire[31:0] m1_addr_i;
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wire[31:0] m1_data_i;
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wire[3:0] m1_sel_i;
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wire m1_req_vld_i;
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wire m1_rsp_rdy_i;
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wire m1_we_i;
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wire m1_req_rdy_o;
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wire m1_rsp_vld_o;
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wire[31:0] m1_data_o;
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// master 2 interface
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wire[31:0] m2_addr_i;
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wire[31:0] m2_data_i;
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wire[3:0] m2_sel_i;
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wire m2_req_vld_i;
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wire m2_rsp_rdy_i;
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wire m2_we_i;
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wire m2_req_rdy_o;
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wire m2_rsp_vld_o;
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wire[31:0] m2_data_o;
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// master 3 interface
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wire[31:0] m3_addr_i;
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wire[31:0] m3_data_i;
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wire[3:0] m3_sel_i;
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wire m3_req_vld_i;
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wire m3_rsp_rdy_i;
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wire m3_we_i;
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wire m3_req_rdy_o;
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wire m3_rsp_vld_o;
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wire[31:0] m3_data_o;
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// slave 0 interface
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wire[31:0] s0_data_i;
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wire s0_req_rdy_i;
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wire s0_rsp_vld_i;
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wire[31:0] s0_addr_o;
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wire[31:0] s0_data_o;
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wire[3:0] s0_sel_o;
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wire s0_req_vld_o;
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wire s0_rsp_rdy_o;
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wire s0_we_o;
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// slave 1 interface
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wire[31:0] s1_data_i;
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wire s1_req_rdy_i;
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wire s1_rsp_vld_i;
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wire[31:0] s1_addr_o;
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wire[31:0] s1_data_o;
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wire[3:0] s1_sel_o;
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wire s1_req_vld_o;
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wire s1_rsp_rdy_o;
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wire s1_we_o;
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// slave 2 interface
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wire[31:0] s2_data_i;
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wire s2_req_rdy_i;
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wire s2_rsp_vld_i;
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wire[31:0] s2_addr_o;
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wire[31:0] s2_data_o;
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wire[3:0] s2_sel_o;
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wire s2_req_vld_o;
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wire s2_rsp_rdy_o;
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wire s2_we_o;
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// slave 3 interface
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wire[31:0] s3_data_i;
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wire s3_req_rdy_i;
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wire s3_rsp_vld_i;
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wire[31:0] s3_addr_o;
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wire[31:0] s3_data_o;
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wire[3:0] s3_sel_o;
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wire s3_req_vld_o;
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wire s3_rsp_rdy_o;
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wire s3_we_o;
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// slave 4 interface
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wire[31:0] s4_data_i;
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wire s4_req_rdy_i;
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wire s4_rsp_vld_i;
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wire[31:0] s4_addr_o;
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wire[31:0] s4_data_o;
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wire[3:0] s4_sel_o;
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wire s4_req_vld_o;
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wire s4_rsp_rdy_o;
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wire s4_we_o;
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// jtag
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wire jtag_halt_req_o;
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wire jtag_reset_req_o;
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wire[4:0] jtag_reg_addr_o;
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wire[31:0] jtag_reg_data_o;
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wire jtag_reg_we_o;
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wire[31:0] jtag_reg_data_i;
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// tinyriscv
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wire[`INT_WIDTH-1:0] int_flag;
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wire rst_n;
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wire jtag_rst_n;
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// timer0
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wire timer0_int;
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// gpio
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wire[1:0] io_in;
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wire[31:0] gpio_ctrl;
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wire[31:0] gpio_data;
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assign int_flag = {{(`INT_WIDTH-1){1'b0}}, timer0_int};
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// 复位控制模块例化
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rst_ctrl u_rst_ctrl(
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.clk(clk),
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.rst_ext_i(rst_ext_i),
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.rst_jtag_i(jtag_reset_req_o),
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.core_rst_n_o(rst_n),
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.jtag_rst_n_o(jtag_rst_n)
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);
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// 低电平点亮LED
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// 低电平表示已经halt住CPU
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assign halted_ind = ~jtag_halt_req_o;
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// tinyriscv处理器核模块例化
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tinyriscv_core u_tinyriscv_core(
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.clk(clk),
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.rst_n(rst_n),
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// 指令总线
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.ibus_addr_o(m0_addr_i),
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.ibus_data_i(m0_data_o),
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.ibus_data_o(m0_data_i),
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.ibus_we_o(m0_we_i),
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.ibus_sel_o(m0_sel_i),
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.ibus_req_valid_o(m0_req_vld_i),
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.ibus_req_ready_i(m0_req_rdy_o),
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.ibus_rsp_valid_i(m0_rsp_vld_o),
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.ibus_rsp_ready_o(m0_rsp_rdy_i),
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// 数据总线
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.dbus_addr_o(m1_addr_i),
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.dbus_data_i(m1_data_o),
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.dbus_data_o(m1_data_i),
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.dbus_we_o(m1_we_i),
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.dbus_sel_o(m1_sel_i),
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.dbus_req_valid_o(m1_req_vld_i),
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.dbus_req_ready_i(m1_req_rdy_o),
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.dbus_rsp_valid_i(m1_rsp_vld_o),
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.dbus_rsp_ready_o(m1_rsp_rdy_i),
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.jtag_halt_i(jtag_halt_req_o),
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.int_i(int_flag)
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);
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// 指令存储器
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rom #(
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.DP(`ROM_DEPTH)
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) u_rom(
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.clk(clk),
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.rst_n(rst_n),
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.addr_i(s0_addr_o),
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.data_i(s0_data_o),
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.sel_i(s0_sel_o),
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.we_i(s0_we_o),
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.data_o(s0_data_i),
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.req_valid_i(s0_req_vld_o),
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.req_ready_o(s0_req_rdy_i),
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.rsp_valid_o(s0_rsp_vld_i),
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.rsp_ready_i(s0_rsp_rdy_o)
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);
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// 数据存储器
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ram #(
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.DP(`RAM_DEPTH)
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) u_ram(
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.clk(clk),
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.rst_n(rst_n),
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.addr_i(s1_addr_o),
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.data_i(s1_data_o),
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.sel_i(s1_sel_o),
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.we_i(s1_we_o),
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.data_o(s1_data_i),
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.req_valid_i(s1_req_vld_o),
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.req_ready_o(s1_req_rdy_i),
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.rsp_valid_o(s1_rsp_vld_i),
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.rsp_ready_i(s1_rsp_rdy_o)
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);
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// timer模块例化
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timer timer_0(
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.clk(clk),
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.rst_n(rst_n),
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.addr_i(s2_addr_o),
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.data_i(s2_data_o),
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.sel_i(s2_sel_o),
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.we_i(s2_we_o),
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.data_o(s2_data_i),
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.req_valid_i(s2_req_vld_o),
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.req_ready_o(s2_req_rdy_i),
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.rsp_valid_o(s2_rsp_vld_i),
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.rsp_ready_i(s2_rsp_rdy_o),
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.int_sig_o(timer0_int)
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);
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// uart模块例化
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uart uart_0(
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.clk(clk),
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.rst_n(rst_n),
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.addr_i(s3_addr_o),
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.data_i(s3_data_o),
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.sel_i(s3_sel_o),
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.we_i(s3_we_o),
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.data_o(s3_data_i),
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.req_valid_i(s3_req_vld_o),
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.req_ready_o(s3_req_rdy_i),
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.rsp_valid_o(s3_rsp_vld_i),
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.rsp_ready_i(s3_rsp_rdy_o),
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.tx_pin(uart_tx_pin),
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.rx_pin(uart_rx_pin)
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);
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// io0
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assign gpio[0] = (gpio_ctrl[1:0] == 2'b01)? gpio_data[0]: 1'bz;
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assign io_in[0] = gpio[0];
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// io1
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assign gpio[1] = (gpio_ctrl[3:2] == 2'b01)? gpio_data[1]: 1'bz;
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assign io_in[1] = gpio[1];
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// gpio模块例化
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gpio gpio_0(
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.clk(clk),
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.rst_n(rst_n),
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.addr_i(s4_addr_o),
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.data_i(s4_data_o),
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.sel_i(s4_sel_o),
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.we_i(s4_we_o),
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.data_o(s4_data_i),
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.req_valid_i(s4_req_vld_o),
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.req_ready_o(s4_req_rdy_i),
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.rsp_valid_o(s4_rsp_vld_i),
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.rsp_ready_i(s4_rsp_rdy_o),
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.io_pin_i(io_in),
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.reg_ctrl(gpio_ctrl),
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.reg_data(gpio_data)
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);
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// jtag模块例化
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jtag_top #(
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.DMI_ADDR_BITS(6),
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.DMI_DATA_BITS(32),
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.DMI_OP_BITS(2)
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) u_jtag_top(
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.clk(clk),
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.jtag_rst_n(jtag_rst_n),
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.jtag_pin_TCK(jtag_TCK),
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.jtag_pin_TMS(jtag_TMS),
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.jtag_pin_TDI(jtag_TDI),
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.jtag_pin_TDO(jtag_TDO),
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.reg_we_o(jtag_reg_we_o),
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.reg_addr_o(jtag_reg_addr_o),
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.reg_wdata_o(jtag_reg_data_o),
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.reg_rdata_i(jtag_reg_data_i),
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.mem_we_o(m2_we_i),
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.mem_addr_o(m2_addr_i),
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.mem_wdata_o(m2_data_i),
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.mem_rdata_i(m2_data_o),
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.mem_sel_o(m2_sel_i),
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.req_valid_o(m2_req_vld_i),
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.req_ready_i(m2_req_rdy_o),
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.rsp_valid_i(m2_rsp_vld_o),
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.rsp_ready_o(m2_rsp_rdy_i),
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.halt_req_o(jtag_halt_req_o),
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.reset_req_o(jtag_reset_req_o)
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);
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// rib总线模块例化
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rib #(
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.MASTER_NUM(3),
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.SLAVE_NUM(5)
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) u_rib(
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.clk(clk),
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.rst_n(rst_n),
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// master 0 interface
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.m0_addr_i(m0_addr_i),
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.m0_data_i(m0_data_i),
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.m0_sel_i(m0_sel_i),
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.m0_req_vld_i(m0_req_vld_i),
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.m0_rsp_rdy_i(m0_rsp_rdy_i),
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.m0_we_i(m0_we_i),
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.m0_req_rdy_o(m0_req_rdy_o),
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.m0_rsp_vld_o(m0_rsp_vld_o),
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.m0_data_o(m0_data_o),
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// master 1 interface
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.m1_addr_i(m1_addr_i),
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.m1_data_i(m1_data_i),
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.m1_sel_i(m1_sel_i),
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.m1_req_vld_i(m1_req_vld_i),
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.m1_rsp_rdy_i(m1_rsp_rdy_i),
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.m1_we_i(m1_we_i),
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.m1_req_rdy_o(m1_req_rdy_o),
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.m1_rsp_vld_o(m1_rsp_vld_o),
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.m1_data_o(m1_data_o),
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// master 2 interface
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.m2_addr_i(m2_addr_i),
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.m2_data_i(m2_data_i),
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.m2_sel_i(m2_sel_i),
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.m2_req_vld_i(m2_req_vld_i),
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.m2_rsp_rdy_i(m2_rsp_rdy_i),
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.m2_we_i(m2_we_i),
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.m2_req_rdy_o(m2_req_rdy_o),
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.m2_rsp_vld_o(m2_rsp_vld_o),
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.m2_data_o(m2_data_o),
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// master 3 interface
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.m3_addr_i(m3_addr_i),
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.m3_data_i(m3_data_i),
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.m3_sel_i(m3_sel_i),
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.m3_req_vld_i(m3_req_vld_i),
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.m3_rsp_rdy_i(m3_rsp_rdy_i),
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.m3_we_i(m3_we_i),
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.m3_req_rdy_o(m3_req_rdy_o),
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.m3_rsp_vld_o(m3_rsp_vld_o),
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.m3_data_o(m3_data_o),
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// slave 0 interface
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.s0_data_i(s0_data_i),
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.s0_req_rdy_i(s0_req_rdy_i),
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.s0_rsp_vld_i(s0_rsp_vld_i),
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.s0_addr_o(s0_addr_o),
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.s0_data_o(s0_data_o),
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.s0_sel_o(s0_sel_o),
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.s0_req_vld_o(s0_req_vld_o),
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.s0_rsp_rdy_o(s0_rsp_rdy_o),
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.s0_we_o(s0_we_o),
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// slave 1 interface
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.s1_data_i(s1_data_i),
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.s1_req_rdy_i(s1_req_rdy_i),
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.s1_rsp_vld_i(s1_rsp_vld_i),
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.s1_addr_o(s1_addr_o),
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.s1_data_o(s1_data_o),
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.s1_sel_o(s1_sel_o),
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.s1_req_vld_o(s1_req_vld_o),
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.s1_rsp_rdy_o(s1_rsp_rdy_o),
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.s1_we_o(s1_we_o),
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// slave 2 interface
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.s2_data_i(s2_data_i),
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.s2_req_rdy_i(s2_req_rdy_i),
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.s2_rsp_vld_i(s2_rsp_vld_i),
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.s2_addr_o(s2_addr_o),
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.s2_data_o(s2_data_o),
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.s2_sel_o(s2_sel_o),
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.s2_req_vld_o(s2_req_vld_o),
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.s2_rsp_rdy_o(s2_rsp_rdy_o),
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.s2_we_o(s2_we_o),
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// slave 3 interface
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.s3_data_i(s3_data_i),
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.s3_req_rdy_i(s3_req_rdy_i),
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.s3_rsp_vld_i(s3_rsp_vld_i),
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.s3_addr_o(s3_addr_o),
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.s3_data_o(s3_data_o),
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.s3_sel_o(s3_sel_o),
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.s3_req_vld_o(s3_req_vld_o),
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.s3_rsp_rdy_o(s3_rsp_rdy_o),
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.s3_we_o(s3_we_o),
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// slave 4 interface
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.s4_data_i(s4_data_i),
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.s4_req_rdy_i(s4_req_rdy_i),
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.s4_rsp_vld_i(s4_rsp_vld_i),
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.s4_addr_o(s4_addr_o),
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.s4_data_o(s4_data_o),
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.s4_sel_o(s4_sel_o),
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.s4_req_vld_o(s4_req_vld_o),
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.s4_rsp_rdy_o(s4_rsp_rdy_o),
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.s4_we_o(s4_we_o)
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);
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endmodule
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