75 lines
2.7 KiB
Verilog
75 lines
2.7 KiB
Verilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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module exu_commit(
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input wire clk,
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input wire rst_n,
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input wire req_muldiv_i,
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input wire muldiv_reg_we_i,
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input wire[4:0] muldiv_reg_waddr_i,
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input wire[31:0] muldiv_reg_wdata_i,
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input wire req_mem_i,
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input wire mem_reg_we_i,
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input wire[4:0] mem_reg_waddr_i,
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input wire[31:0] mem_reg_wdata_i,
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input wire req_csr_i,
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input wire csr_reg_we_i,
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input wire[4:0] csr_reg_waddr_i,
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input wire[31:0] csr_reg_wdata_i,
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input wire req_bjp_i,
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input wire bjp_reg_we_i,
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input wire[31:0] bjp_reg_wdata_i,
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input wire[4:0] bjp_reg_waddr_i,
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input wire rd_we_i,
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input wire[4:0] rd_waddr_i,
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input wire[31:0] alu_reg_wdata_i,
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output wire reg_we_o,
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output wire[4:0] reg_waddr_o,
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output wire[31:0] reg_wdata_o
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);
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wire use_alu_res = (~req_muldiv_i) &
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(~req_mem_i) &
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(~req_csr_i) &
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(~req_bjp_i);
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assign reg_we_o = muldiv_reg_we_i | mem_reg_we_i | csr_reg_we_i | use_alu_res | bjp_reg_we_i;
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assign reg_waddr_o = ({5{muldiv_reg_we_i}} & muldiv_reg_waddr_i) |
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({5{mem_reg_we_i}} & mem_reg_waddr_i) |
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({5{csr_reg_we_i}} & csr_reg_waddr_i) |
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({5{bjp_reg_we_i}} & bjp_reg_waddr_i) |
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({5{rd_we_i}} & rd_waddr_i);
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assign reg_wdata_o = ({32{muldiv_reg_we_i}} & muldiv_reg_wdata_i) |
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({32{mem_reg_we_i}} & mem_reg_wdata_i) |
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({32{csr_reg_we_i}} & csr_reg_wdata_i) |
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({32{bjp_reg_we_i}} & bjp_reg_wdata_i) |
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({32{use_alu_res}} & alu_reg_wdata_i);
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endmodule
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