123 lines
4.8 KiB
Verilog
123 lines
4.8 KiB
Verilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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module exu_mem(
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input wire clk,
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input wire rst_n,
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input req_mem_i,
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input wire[31:0] mem_addr_i,
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input wire[31:0] mem_rs2_data_i,
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input wire[31:0] mem_rdata_i,
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input wire mem_req_ready_i,
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input wire mem_rsp_valid_i,
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input wire mem_op_lb_i,
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input wire mem_op_lh_i,
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input wire mem_op_lw_i,
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input wire mem_op_lbu_i,
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input wire mem_op_lhu_i,
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input wire mem_op_sb_i,
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input wire mem_op_sh_i,
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input wire mem_op_sw_i,
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output wire mem_stall_o,
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output wire[31:0] mem_addr_o,
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output wire[31:0] mem_wdata_o,
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output wire mem_reg_we_o,
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output wire mem_mem_we_o,
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output wire[3:0] mem_sel_o,
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output wire mem_req_valid_o,
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output wire mem_rsp_ready_o
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);
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wire[1:0] mem_addr_index = mem_addr_i[1:0];
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wire mem_addr_index00 = (mem_addr_index == 2'b00);
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wire mem_addr_index01 = (mem_addr_index == 2'b01);
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wire mem_addr_index10 = (mem_addr_index == 2'b10);
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wire mem_addr_index11 = (mem_addr_index == 2'b11);
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assign mem_sel_o[0] = mem_addr_index00 | mem_op_sw_i;
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assign mem_sel_o[1] = mem_addr_index01 | (mem_op_sh_i & mem_addr_index00) | mem_op_sw_i;
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assign mem_sel_o[2] = mem_addr_index10 | mem_op_sw_i;
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assign mem_sel_o[3] = mem_addr_index11 | (mem_op_sh_i & mem_addr_index10) | mem_op_sw_i;
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// store操作
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wire[31:0] sb_res = ({32{mem_addr_index00}} & {24'h0, mem_rs2_data_i[7:0]}) |
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({32{mem_addr_index01}} & {16'h0, mem_rs2_data_i[7:0], 8'h0}) |
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({32{mem_addr_index10}} & {8'h0, mem_rs2_data_i[7:0], 16'h0}) |
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({32{mem_addr_index11}} & {mem_rs2_data_i[7:0], 24'h0});
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wire[31:0] sh_res = ({32{mem_addr_index00}} & {16'h0, mem_rs2_data_i[15:0]}) |
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({32{mem_addr_index10}} & {mem_rs2_data_i[15:0], 16'h0});
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wire[31:0] sw_res = mem_rs2_data_i;
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// load操作
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wire[31:0] lb_res = ({32{mem_addr_index00}} & {{24{mem_op_lb_i & mem_rdata_i[7]}}, mem_rdata_i[7:0]}) |
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({32{mem_addr_index01}} & {{24{mem_op_lb_i & mem_rdata_i[15]}}, mem_rdata_i[15:8]}) |
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({32{mem_addr_index10}} & {{24{mem_op_lb_i & mem_rdata_i[23]}}, mem_rdata_i[23:16]}) |
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({32{mem_addr_index11}} & {{24{mem_op_lb_i & mem_rdata_i[31]}}, mem_rdata_i[31:24]});
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wire[31:0] lh_res = ({32{mem_addr_index00}} & {{24{mem_op_lh_i & mem_rdata_i[15]}}, mem_rdata_i[15:0]}) |
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({32{mem_addr_index10}} & {{24{mem_op_lh_i & mem_rdata_i[31]}}, mem_rdata_i[31:16]});
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wire[31:0] lw_res = mem_rdata_i;
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// 写回内存或者寄存器的数据
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assign mem_wdata_o = ({32{mem_op_sb_i}} & sb_res) |
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({32{mem_op_sh_i}} & sh_res) |
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({32{mem_op_sw_i}} & sw_res) |
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({32{mem_op_lb_i | mem_op_lbu_i}} & lb_res) |
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({32{mem_op_lh_i | mem_op_lhu_i}} & lh_res) |
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({32{mem_op_lw_i}} & lw_res);
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wire mem_req_hsked = (mem_req_valid_o & mem_req_ready_i);
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wire mem_rsp_hsked = (mem_rsp_valid_i & mem_rsp_ready_o);
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reg mem_rsp_hsked_r;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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mem_rsp_hsked_r <= 1'b0;
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end else begin
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mem_rsp_hsked_r <= mem_rsp_hsked & (~mem_rsp_hsked_r);
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end
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end
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assign mem_rsp_ready_o = 1'b1;
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// 请求访问总线
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assign mem_req_valid_o = req_mem_i;
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// 暂停流水线
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assign mem_stall_o = req_mem_i & (~mem_rsp_hsked_r);
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// 读、写内存地址
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assign mem_addr_o = mem_addr_i;
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// 写寄存器使能，收到ack时数据才有效
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assign mem_reg_we_o = (mem_op_lb_i | mem_op_lh_i | mem_op_lw_i | mem_op_lbu_i | mem_op_lhu_i) & mem_rsp_hsked_r;
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// 写内存使能
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assign mem_mem_we_o = (mem_op_sb_i | mem_op_sh_i | mem_op_sw_i) & mem_rsp_hsked_r;
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endmodule
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