tinyriscv/tests/isa/generated/rv32ui-p-auipc.verilog

16 lines
621 B
Plaintext

@00000000
13 0D 00 00 93 0D 00 00 17 25 00 00 13 05 C5 71
EF 05 40 00 33 05 B5 40 B7 2E 00 00 93 8E 0E 71
93 01 20 00 63 14 D5 03 17 E5 FF FF 13 05 C5 8F
EF 05 40 00 33 05 B5 40 B7 EE FF FF 93 8E 0E 8F
93 01 30 00 63 14 D5 01 63 18 30 00 13 0D 10 00
93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00
6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
@00000080
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00