tinyriscv/tests/isa/generated/rv32ui-p-lui.verilog

17 lines
646 B
Plaintext

@00000000
13 0D 00 00 93 0D 00 00 B7 00 00 00 93 0E 00 00
93 01 20 00 63 9A D0 05 B7 F0 FF FF 93 D0 10 40
93 0E 00 80 93 01 30 00 63 90 D0 05 B7 F0 FF 7F
93 D0 40 41 93 0E F0 7F 93 01 40 00 63 96 D0 03
B7 00 00 80 93 D0 40 41 93 0E 00 80 93 01 50 00
63 9C D0 01 37 00 00 80 93 0E 00 00 93 01 60 00
63 14 D0 01 63 18 30 00 13 0D 10 00 93 0D 00 00
6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00
00 00 00 00
@000000C0
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00