tinyriscv/tests/isa/generated/rv32um-p-divu.verilog

25 lines
1.0 KiB
Plaintext

@00000000
13 0D 00 00 93 0D 00 00 93 00 40 01 13 01 60 00
33 DF 20 02 93 0E 30 00 93 01 20 00 63 16 DF 0D
93 00 C0 FE 13 01 60 00 33 DF 20 02 B7 BE AA 2A
93 8E 7E AA 93 01 30 00 63 18 DF 0B 93 00 40 01
13 01 A0 FF 33 DF 20 02 93 0E 00 00 93 01 40 00
63 1C DF 09 93 00 C0 FE 13 01 A0 FF 33 DF 20 02
93 0E 00 00 93 01 50 00 63 10 DF 09 B7 00 00 80
13 01 10 00 33 DF 20 02 B7 0E 00 80 93 01 60 00
63 14 DF 07 B7 00 00 80 13 01 F0 FF 33 DF 20 02
93 0E 00 00 93 01 70 00 63 18 DF 05 B7 00 00 80
13 01 00 00 33 DF 20 02 93 0E F0 FF 93 01 80 00
63 1C DF 03 93 00 10 00 13 01 00 00 33 DF 20 02
93 0E F0 FF 93 01 90 00 63 10 DF 03 93 00 00 00
13 01 00 00 33 DF 20 02 93 0E F0 FF 93 01 A0 00
63 14 DF 01 63 18 30 00 13 0D 10 00 93 0D 00 00
6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00
00 00 00 00
@00000140
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00