325 lines
12 KiB
Verilog
325 lines
12 KiB
Verilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// clk = 50MHz时对应的波特率分频系数
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`define UART_BAUD_115200 32'h1B8
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// 串口寄存器地址
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`define UART_CTRL_REG 32'h30000000
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`define UART_STATUS_REG 32'h30000004
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`define UART_BAUD_REG 32'h30000008
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`define UART_TX_REG 32'h3000000c
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`define UART_RX_REG 32'h30000010
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`define UART_TX_BUSY_FLAG 32'h1
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`define UART_RX_OVER_FLAG 32'h2
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// 第一个包的大小
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`define UART_FIRST_PACKET_LEN 8'd131
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// 其他包的大小(每次烧写的字节数)
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`define UART_REMAIN_PACKET_LEN 8'd131
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`define UART_RESP_ACK 32'h6
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`define UART_RESP_NAK 32'h15
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// 烧写起始地址
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`define ROM_START_ADDR 32'h0
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// 串口更新固件模块
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module uart_debug(
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input wire clk, // 时钟信号
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input wire rst, // 复位信号
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input wire debug_en_i, // 模块使能信号
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output wire req_o,
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output reg mem_we_o,
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output reg[31:0] mem_addr_o,
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output reg[31:0] mem_wdata_o,
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input wire[31:0] mem_rdata_i
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);
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// 状态
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localparam S_IDLE = 1;
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localparam S_INIT_UART_BAUD = 2;
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localparam S_CLEAR_UART_RX_OVER_FLAG = 3;
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localparam S_WAIT_BYTE = 4;
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localparam S_WAIT_BYTE2 = 5;
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localparam S_GET_BYTE = 6;
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localparam S_REC_FIRST_PACKET = 7;
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localparam S_REC_REMAIN_PACKET = 8;
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localparam S_SEND_ACK = 9;
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localparam S_SEND_NAK = 10;
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localparam S_CRC_START = 11;
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localparam S_CRC_CALC = 12;
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localparam S_CRC_END = 13;
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localparam S_WRITE_MEM = 14;
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reg[3:0] state;
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// 存放串口接收到的数据
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reg[7:0] rx_data[0:131];
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reg[7:0] rec_bytes_index;
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reg[7:0] need_to_rec_bytes;
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reg[15:0] remain_packet_count;
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reg[31:0] fw_file_size;
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reg[31:0] write_mem_addr;
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reg[31:0] write_mem_data;
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reg[7:0] write_mem_byte_index;
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reg[15:0] crc_result;
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reg[3:0] crc_bit_index;
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reg[7:0] crc_byte_index;
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// 向总线请求信号
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assign req_o = (rst == 1'b1 && debug_en_i == 1'b1)? 1'b1: 1'b0;
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always @ (posedge clk) begin
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if (rst == 1'b0 || debug_en_i == 1'b0) begin
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mem_addr_o <= 32'h0;
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mem_we_o <= 1'b0;
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mem_wdata_o <= 32'h0;
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state <= S_IDLE;
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remain_packet_count <= 16'h0;
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end else begin
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case (state)
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S_IDLE: begin
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mem_addr_o <= `UART_CTRL_REG;
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mem_wdata_o <= 32'h3;
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mem_we_o <= 1'b1;
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state <= S_INIT_UART_BAUD;
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end
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S_INIT_UART_BAUD: begin
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mem_addr_o <= `UART_BAUD_REG;
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mem_wdata_o <= `UART_BAUD_115200;
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mem_we_o <= 1'b1;
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state <= S_REC_FIRST_PACKET;
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end
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S_REC_FIRST_PACKET: begin
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remain_packet_count <= 16'h0;
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mem_addr_o <= 32'h0;
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mem_we_o <= 1'b0;
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mem_wdata_o <= 32'h0;
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state <= S_CLEAR_UART_RX_OVER_FLAG;
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end
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S_REC_REMAIN_PACKET: begin
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mem_addr_o <= 32'h0;
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mem_we_o <= 1'b0;
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mem_wdata_o <= 32'h0;
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state <= S_CLEAR_UART_RX_OVER_FLAG;
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end
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S_CLEAR_UART_RX_OVER_FLAG: begin
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mem_addr_o <= `UART_STATUS_REG;
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mem_wdata_o <= 32'h0;
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mem_we_o <= 1'b1;
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state <= S_WAIT_BYTE;
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end
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S_WAIT_BYTE: begin
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mem_addr_o <= `UART_STATUS_REG;
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mem_wdata_o <= 32'h0;
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mem_we_o <= 1'b0;
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state <= S_WAIT_BYTE2;
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end
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S_WAIT_BYTE2: begin
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if ((mem_rdata_i & `UART_RX_OVER_FLAG) == `UART_RX_OVER_FLAG) begin
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mem_addr_o <= `UART_RX_REG;
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mem_wdata_o <= 32'h0;
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mem_we_o <= 1'b0;
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state <= S_GET_BYTE;
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end
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end
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S_GET_BYTE: begin
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if (rec_bytes_index == (need_to_rec_bytes - 1'b1)) begin
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state <= S_CRC_START;
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end else begin
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state <= S_CLEAR_UART_RX_OVER_FLAG;
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end
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end
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S_CRC_START: begin
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state <= S_CRC_CALC;
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end
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S_CRC_CALC: begin
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if ((crc_byte_index == need_to_rec_bytes - 2) && crc_bit_index == 4'h8) begin
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state <= S_CRC_END;
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end
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end
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S_CRC_END: begin
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if (crc_result == {rx_data[need_to_rec_bytes - 1], rx_data[need_to_rec_bytes - 2]}) begin
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if (need_to_rec_bytes == `UART_FIRST_PACKET_LEN && remain_packet_count == 16'h0) begin
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remain_packet_count <= {7'h0, fw_file_size[31:7]} + 1'b1;
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state <= S_SEND_ACK;
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end else begin
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remain_packet_count <= remain_packet_count - 1'b1;
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state <= S_WRITE_MEM;
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end
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end else begin
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state <= S_SEND_NAK;
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end
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end
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S_WRITE_MEM: begin
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if (write_mem_byte_index == (need_to_rec_bytes + 2)) begin
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state <= S_SEND_ACK;
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end else begin
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mem_addr_o <= write_mem_addr;
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mem_wdata_o <= write_mem_data;
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mem_we_o <= 1'b1;
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end
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end
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S_SEND_ACK: begin
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mem_addr_o <= `UART_TX_REG;
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mem_wdata_o <= `UART_RESP_ACK;
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mem_we_o <= 1'b1;
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if (remain_packet_count > 0) begin
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state <= S_REC_REMAIN_PACKET;
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end else begin
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state <= S_REC_FIRST_PACKET;
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end
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end
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S_SEND_NAK: begin
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mem_addr_o <= `UART_TX_REG;
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mem_wdata_o <= `UART_RESP_NAK;
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mem_we_o <= 1'b1;
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if (remain_packet_count > 0) begin
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state <= S_REC_REMAIN_PACKET;
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end else begin
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state <= S_REC_FIRST_PACKET;
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end
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end
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endcase
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end
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end
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// 数据包的大小
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always @ (posedge clk) begin
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if (rst == 1'b0 || debug_en_i == 1'b0) begin
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need_to_rec_bytes <= 8'h0;
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end else begin
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case (state)
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S_REC_FIRST_PACKET: begin
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need_to_rec_bytes <= `UART_FIRST_PACKET_LEN;
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end
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S_REC_REMAIN_PACKET: begin
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need_to_rec_bytes <= `UART_REMAIN_PACKET_LEN;
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end
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endcase
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end
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end
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// 读接收到的串口数据
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always @ (posedge clk) begin
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if (rst == 1'b0 || debug_en_i == 1'b0) begin
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rec_bytes_index <= 8'h0;
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end else begin
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case (state)
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S_GET_BYTE: begin
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rx_data[rec_bytes_index] <= mem_rdata_i[7:0];
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rec_bytes_index <= rec_bytes_index + 1'b1;
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end
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S_REC_FIRST_PACKET: begin
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rec_bytes_index <= 8'h0;
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end
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S_REC_REMAIN_PACKET: begin
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rec_bytes_index <= 8'h0;
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end
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endcase
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end
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end
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// 固件大小
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always @ (posedge clk) begin
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if (rst == 1'b0 || debug_en_i == 1'b0) begin
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fw_file_size <= 32'h0;
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end else begin
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case (state)
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S_CRC_START: begin
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fw_file_size <= {rx_data[61], rx_data[62], rx_data[63], rx_data[64]};
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end
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endcase
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end
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end
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// 烧写固件
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always @ (posedge clk) begin
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if (rst == 1'b0 || debug_en_i == 1'b0) begin
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write_mem_addr <= 32'h0;
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write_mem_data <= 32'h0;
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write_mem_byte_index <= 8'h0;
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end else begin
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case (state)
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S_REC_FIRST_PACKET: begin
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write_mem_addr <= `ROM_START_ADDR;
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write_mem_data <= 32'h0;
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write_mem_byte_index <= 8'h0;
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end
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S_CRC_END: begin
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write_mem_data <= {rx_data[4], rx_data[3], rx_data[2], rx_data[1]};
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write_mem_byte_index <= 8'h5;
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if (write_mem_addr > 0)
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write_mem_addr <= write_mem_addr - 4;
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end
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S_WRITE_MEM: begin
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write_mem_addr <= write_mem_addr + 4;
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write_mem_data <= {rx_data[write_mem_byte_index + 3], rx_data[write_mem_byte_index + 2], rx_data[write_mem_byte_index + 1], rx_data[write_mem_byte_index]};
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write_mem_byte_index <= write_mem_byte_index + 4;
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end
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endcase
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end
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end
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// CRC计算
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always @ (posedge clk) begin
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if (rst == 1'b0 || debug_en_i == 1'b0) begin
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crc_result <= 16'h0;
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crc_bit_index <= 4'h0;
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crc_byte_index <= 8'h0;
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end else begin
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case (state)
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S_CRC_START: begin
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crc_result <= 16'hffff;
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crc_bit_index <= 4'h0;
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crc_byte_index <= 8'h1;
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end
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S_CRC_CALC: begin
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if (crc_bit_index == 4'h0) begin
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crc_result <= crc_result ^ rx_data[crc_byte_index];
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crc_byte_index <= crc_byte_index + 1'b1;
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crc_bit_index <= crc_bit_index + 1'b1;
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end else begin
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if (crc_bit_index < 4'h9) begin
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crc_bit_index <= crc_bit_index + 1'b1;
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if (crc_result[0] == 1'b1) begin
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crc_result <= {1'b0, crc_result[15:1]} ^ 16'ha001;
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end else begin
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crc_result <= {1'b0, crc_result[15:1]};
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end
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end else begin
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crc_bit_index <= 4'h0;
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end
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end
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end
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endcase
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end
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end
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endmodule
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