47 lines
1.7 KiB
Systemverilog
47 lines
1.7 KiB
Systemverilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// 将输入打DP拍后输出
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module gen_ticks_sync #(
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parameter DP = 2,
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parameter DW = 32)(
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input wire rst_n,
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input wire clk,
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input wire[DW-1:0] din,
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output wire[DW-1:0] dout
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);
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wire[DW-1:0] sync_dat[DP-1:0];
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genvar i;
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generate
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for (i = 0; i < DP; i = i + 1) begin: ticks_sync
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if (i == 0) begin: dp_is_0
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gen_rst_0_dff #(DW) rst_0_dff(clk, rst_n, din, sync_dat[0]);
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end else begin: dp_is_not_0
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gen_rst_0_dff #(DW) rst_0_dff(clk, rst_n, sync_dat[i-1], sync_dat[i]);
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end
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end
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endgenerate
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assign dout = sync_dat[DP-1];
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endmodule
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