43 lines
1.5 KiB
Systemverilog
43 lines
1.5 KiB
Systemverilog
/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module csr #(
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parameter RESET_VAL = 32'h0
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)(
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input wire clk,
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input wire rst_n,
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input wire [31:0] wdata_i,
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input wire we_i,
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output wire [31:0] rdata_o
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);
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reg[31:0] rdata_q;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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rdata_q <= RESET_VAL;
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end else if (we_i) begin
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rdata_q <= wdata_i;
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end
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end
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assign rdata_o = rdata_q;
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endmodule
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