|
clint.v
|
use = instead of <= in combination logic
|
2020-05-02 11:58:44 +08:00 |
|
csr_reg.v
|
use = instead of <= in combination logic
|
2020-05-02 11:58:44 +08:00 |
|
ctrl.v
|
use = instead of <= in combination logic
|
2020-05-02 11:58:44 +08:00 |
|
defines.v
|
add ECALL inst
|
2020-04-25 17:11:53 +08:00 |
|
div.v
|
stop div when interrupt assert
|
2020-04-25 17:04:44 +08:00 |
|
ex.v
|
use = instead of <= in combination logic
|
2020-05-02 11:58:44 +08:00 |
|
id.v
|
use = instead of <= in combination logic
|
2020-05-02 11:58:44 +08:00 |
|
id_ex.v
|
add code comments
|
2020-04-18 20:14:37 +08:00 |
|
if_id.v
|
add code comments
|
2020-04-18 20:14:37 +08:00 |
|
pc_reg.v
|
add code comments
|
2020-04-18 20:14:37 +08:00 |
|
regs.v
|
add code comments
|
2020-04-18 20:14:37 +08:00 |
|
rib.v
|
use = instead of <= in combination logic
|
2020-05-02 11:58:44 +08:00 |
|
tinyriscv.v
|
add signal
|
2020-04-25 17:15:46 +08:00 |
837af2c977