289 lines
12 KiB
Verilog
289 lines
12 KiB
Verilog
/*
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Copyright 2019 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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// 译码模块
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// 纯组合逻辑电路
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module id(
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input wire rst,
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// from if_id
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input wire[`InstBus] inst_i, // 指令内容
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input wire[`InstAddrBus] inst_addr_i, // 指令地址
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// from regs
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input wire[`RegBus] reg1_rdata_i, // 通用寄存器1输入数据
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input wire[`RegBus] reg2_rdata_i, // 通用寄存器2输入数据
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// from csr reg
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input wire[`RegBus] csr_rdata_i, // CSR寄存器输入数据
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// from ex
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input wire ex_jump_flag_i, // 跳转标志
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// to regs
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output reg[`RegAddrBus] reg1_raddr_o, // 读通用寄存器1地址
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output reg[`RegAddrBus] reg2_raddr_o, // 读通用寄存器2地址
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// to csr reg
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output reg[`MemAddrBus] csr_raddr_o, // 读CSR寄存器地址
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output wire mem_req_o, // 向总线请求访问内存标志
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// to ex
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output reg[`InstBus] inst_o, // 指令内容
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output reg[`InstAddrBus] inst_addr_o, // 指令地址
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output reg[`RegBus] reg1_rdata_o, // 通用寄存器1数据
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output reg[`RegBus] reg2_rdata_o, // 通用寄存器2数据
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output reg reg_we_o, // 写通用寄存器标志
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output reg[`RegAddrBus] reg_waddr_o, // 写通用寄存器地址
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output reg csr_we_o, // 写CSR寄存器标志
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output reg[`RegBus] csr_rdata_o, // CSR寄存器数据
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output reg[`MemAddrBus] csr_waddr_o // 写CSR寄存器地址
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);
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wire[6:0] opcode = inst_i[6:0];
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wire[2:0] funct3 = inst_i[14:12];
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wire[6:0] funct7 = inst_i[31:25];
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wire[4:0] rd = inst_i[11:7];
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wire[4:0] rs1 = inst_i[19:15];
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wire[4:0] rs2 = inst_i[24:20];
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reg mem_req;
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// 跳转时不向总线请求访问内存
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assign mem_req_o = ((mem_req == `RIB_REQ) && (ex_jump_flag_i == `JumpDisable));
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always @ (*) begin
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if (rst == `RstEnable) begin
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reg1_raddr_o = `ZeroReg;
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reg2_raddr_o = `ZeroReg;
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csr_raddr_o = `ZeroWord;
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inst_o = `INST_NOP;
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inst_addr_o = `ZeroWord;
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reg1_rdata_o = `ZeroWord;
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reg2_rdata_o = `ZeroWord;
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csr_rdata_o = `ZeroWord;
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reg_we_o = `WriteDisable;
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csr_we_o = `WriteDisable;
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reg_waddr_o = `ZeroReg;
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csr_waddr_o = `ZeroWord;
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mem_req = `RIB_NREQ;
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end else begin
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inst_o = inst_i;
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inst_addr_o = inst_addr_i;
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reg1_rdata_o = reg1_rdata_i;
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reg2_rdata_o = reg2_rdata_i;
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csr_rdata_o = csr_rdata_i;
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mem_req = `RIB_NREQ;
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csr_raddr_o = `ZeroWord;
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csr_waddr_o = `ZeroWord;
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csr_we_o = `WriteDisable;
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case (opcode)
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`INST_TYPE_I: begin
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case (funct3)
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`INST_ADDI, `INST_SLTI, `INST_SLTIU, `INST_XORI, `INST_ORI, `INST_ANDI, `INST_SLLI, `INST_SRI: begin
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reg_we_o = `WriteEnable;
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reg_waddr_o = rd;
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reg1_raddr_o = rs1;
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reg2_raddr_o = `ZeroReg;
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end
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default: begin
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reg_we_o = `WriteDisable;
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reg_waddr_o = `ZeroReg;
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reg1_raddr_o = `ZeroReg;
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reg2_raddr_o = `ZeroReg;
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end
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endcase
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end
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`INST_TYPE_R_M: begin
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if ((funct7 == 7'b0000000) || (funct7 == 7'b0100000)) begin
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case (funct3)
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`INST_ADD_SUB, `INST_SLL, `INST_SLT, `INST_SLTU, `INST_XOR, `INST_SR, `INST_OR, `INST_AND: begin
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reg_we_o = `WriteEnable;
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reg_waddr_o = rd;
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reg1_raddr_o = rs1;
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reg2_raddr_o = rs2;
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end
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default: begin
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reg_we_o = `WriteDisable;
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reg_waddr_o = `ZeroReg;
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reg1_raddr_o = `ZeroReg;
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reg2_raddr_o = `ZeroReg;
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end
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endcase
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end else if (funct7 == 7'b0000001) begin
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case (funct3)
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`INST_MUL, `INST_MULHU, `INST_MULH, `INST_MULHSU: begin
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reg_we_o = `WriteEnable;
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reg_waddr_o = rd;
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reg1_raddr_o = rs1;
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reg2_raddr_o = rs2;
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end
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`INST_DIV, `INST_DIVU, `INST_REM, `INST_REMU: begin
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reg_we_o = `WriteDisable;
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reg_waddr_o = rd;
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reg1_raddr_o = rs1;
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reg2_raddr_o = rs2;
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end
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default: begin
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reg_we_o = `WriteDisable;
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reg_waddr_o = `ZeroReg;
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reg1_raddr_o = `ZeroReg;
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reg2_raddr_o = `ZeroReg;
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end
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endcase
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end else begin
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reg_we_o = `WriteDisable;
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reg_waddr_o = `ZeroReg;
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reg1_raddr_o = `ZeroReg;
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reg2_raddr_o = `ZeroReg;
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end
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end
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`INST_TYPE_L: begin
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case (funct3)
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`INST_LB, `INST_LH, `INST_LW, `INST_LBU, `INST_LHU: begin
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reg1_raddr_o = rs1;
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reg2_raddr_o = `ZeroReg;
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reg_we_o = `WriteEnable;
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reg_waddr_o = rd;
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mem_req = `RIB_REQ;
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end
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default: begin
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reg1_raddr_o = `ZeroReg;
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reg2_raddr_o = `ZeroReg;
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reg_we_o = `WriteDisable;
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reg_waddr_o = `ZeroReg;
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end
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endcase
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end
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`INST_TYPE_S: begin
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case (funct3)
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`INST_SB, `INST_SW, `INST_SH: begin
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reg1_raddr_o = rs1;
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reg2_raddr_o = rs2;
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reg_we_o = `WriteDisable;
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reg_waddr_o = `ZeroReg;
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mem_req = `RIB_REQ;
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end
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default: begin
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reg1_raddr_o = `ZeroReg;
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reg2_raddr_o = `ZeroReg;
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reg_we_o = `WriteDisable;
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reg_waddr_o = `ZeroReg;
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end
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endcase
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end
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`INST_TYPE_B: begin
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case (funct3)
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`INST_BEQ, `INST_BNE, `INST_BLT, `INST_BGE, `INST_BLTU, `INST_BGEU: begin
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reg1_raddr_o = rs1;
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reg2_raddr_o = rs2;
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reg_we_o = `WriteDisable;
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reg_waddr_o = `ZeroReg;
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end
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default: begin
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reg1_raddr_o = `ZeroReg;
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reg2_raddr_o = `ZeroReg;
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reg_we_o = `WriteDisable;
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reg_waddr_o = `ZeroReg;
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end
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endcase
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end
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`INST_JAL: begin
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reg_we_o = `WriteEnable;
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reg_waddr_o = rd;
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reg1_raddr_o = `ZeroReg;
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reg2_raddr_o = `ZeroReg;
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end
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`INST_JALR: begin
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reg_we_o = `WriteEnable;
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reg1_raddr_o = rs1;
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reg2_raddr_o = `ZeroReg;
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reg_waddr_o = rd;
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end
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`INST_LUI: begin
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reg_we_o = `WriteEnable;
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reg_waddr_o = rd;
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reg1_raddr_o = `ZeroReg;
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reg2_raddr_o = `ZeroReg;
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end
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`INST_AUIPC: begin
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reg_we_o = `WriteEnable;
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reg_waddr_o = rd;
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reg1_raddr_o = `ZeroReg;
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reg2_raddr_o = `ZeroReg;
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end
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`INST_NOP: begin
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reg_we_o = `WriteDisable;
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reg_waddr_o = `ZeroReg;
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reg1_raddr_o = `ZeroReg;
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reg2_raddr_o = `ZeroReg;
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end
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`INST_FENCE: begin
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reg_we_o = `WriteDisable;
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reg_waddr_o = `ZeroReg;
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reg1_raddr_o = `ZeroReg;
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reg2_raddr_o = `ZeroReg;
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end
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`INST_CSR: begin
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reg_we_o = `WriteDisable;
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reg_waddr_o = `ZeroReg;
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reg1_raddr_o = `ZeroReg;
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reg2_raddr_o = `ZeroReg;
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csr_raddr_o = {20'h0, inst_i[31:20]};
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csr_waddr_o = {20'h0, inst_i[31:20]};
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case (funct3)
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`INST_CSRRW, `INST_CSRRS, `INST_CSRRC: begin
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reg1_raddr_o = rs1;
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reg2_raddr_o = `ZeroReg;
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reg_we_o = `WriteEnable;
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reg_waddr_o = rd;
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csr_we_o = `WriteEnable;
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end
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`INST_CSRRWI, `INST_CSRRSI, `INST_CSRRCI: begin
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reg1_raddr_o = `ZeroReg;
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reg2_raddr_o = `ZeroReg;
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reg_we_o = `WriteEnable;
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reg_waddr_o = rd;
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csr_we_o = `WriteEnable;
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end
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default: begin
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reg_we_o = `WriteDisable;
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reg_waddr_o = `ZeroReg;
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reg1_raddr_o = `ZeroReg;
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reg2_raddr_o = `ZeroReg;
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csr_we_o = `WriteDisable;
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end
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endcase
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end
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default: begin
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reg_we_o = `WriteDisable;
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reg_waddr_o = `ZeroReg;
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reg1_raddr_o = `ZeroReg;
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reg2_raddr_o = `ZeroReg;
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end
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endcase
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end
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end
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endmodule
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