tinyriscv/sim
liangkangnan 07b33baf94 perips: add spi master
Signed-off-by: liangkangnan <liangkangnan@163.com>
2020-05-05 18:31:08 +08:00
..
inst.data reorganize example and optimize interrupt 2020-04-11 19:03:49 +08:00
out.vvp reorganize example and optimize interrupt 2020-04-11 19:03:49 +08:00
sim_default_nowave.bat perips: add spi master 2020-05-05 18:31:08 +08:00
sim_new_nowave.bat perips: add spi master 2020-05-05 18:31:08 +08:00
test_all_isa.py update 2020-03-29 23:19:14 +08:00
tinyriscv_soc_tb.v update 2020-03-29 23:19:14 +08:00
tinyriscv_soc_tb.vcd reorganize example and optimize interrupt 2020-04-11 19:03:49 +08:00