119 lines
3.6 KiB
Verilog
119 lines
3.6 KiB
Verilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "../core/defines.v"
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// 32 bits count up timer module
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module timer(
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input wire clk,
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input wire rst,
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input wire[31:0] data_i,
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input wire[31:0] addr_i,
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input wire we_i,
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output reg[31:0] data_o,
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output wire int_sig_o
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);
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localparam REG_CTRL = 4'h0;
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localparam REG_COUNT = 4'h4;
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localparam REG_VALUE = 4'h8;
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// [0]: timer enable
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// [1]: timer int enable
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// [2]: timer int pending, write 1 to clear it
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// addr offset: 0x00
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reg[31:0] timer_ctrl;
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// timer current count, read only
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// addr offset: 0x04
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reg[31:0] timer_count;
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// timer expired value
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// addr offset: 0x08
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reg[31:0] timer_value;
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assign int_sig_o = ((timer_ctrl[2] == 1'b1) && (timer_ctrl[1] == 1'b1))? `INT_ASSERT: `INT_DEASSERT;
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// counter
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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timer_count <= `ZeroWord;
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end else begin
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if (timer_ctrl[0] == 1'b1) begin
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timer_count <= timer_count + 1'b1;
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if (timer_count >= timer_value) begin
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timer_count <= `ZeroWord;
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end
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end else begin
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timer_count <= `ZeroWord;
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end
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end
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end
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// write regs
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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timer_ctrl <= `ZeroWord;
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timer_value <= `ZeroWord;
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end else begin
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if (we_i == `WriteEnable) begin
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case (addr_i[3:0])
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REG_CTRL: begin
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timer_ctrl <= {data_i[31:3], (timer_ctrl[2] & (~data_i[2])), data_i[1:0]};
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end
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REG_VALUE: begin
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timer_value <= data_i;
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end
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endcase
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end else begin
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if ((timer_ctrl[0] == 1'b1) && (timer_count >= timer_value)) begin
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timer_ctrl[0] <= 1'b0;
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timer_ctrl[2] <= 1'b1;
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end
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end
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end
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end
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// read regs
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always @ (*) begin
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if (rst == `RstEnable) begin
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data_o = `ZeroWord;
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end else begin
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case (addr_i[3:0])
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REG_VALUE: begin
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data_o = timer_value;
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end
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REG_CTRL: begin
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data_o = timer_ctrl;
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end
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REG_COUNT: begin
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data_o = timer_count;
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end
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default: begin
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data_o = `ZeroWord;
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end
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endcase
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end
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end
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endmodule
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