101 lines
3.6 KiB
C
101 lines
3.6 KiB
C
// Generated register defines for i2c
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// Copyright information found in source file:
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// Copyright lowRISC contributors.
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// Licensing information found in source file:
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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#ifndef _I2C_REG_DEFS_
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#define _I2C_REG_DEFS_
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Register width
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#define I2C_PARAM_REG_WIDTH 32
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#define I2C0_BASE_ADDR (0x06000000)
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#define I2C1_BASE_ADDR (0x0B000000)
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#define I2C0 (I2C0_BASE_ADDR)
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#define I2C1 (I2C1_BASE_ADDR)
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#define I2C_REG(base, offset) (*((volatile uint32_t *)(base + offset)))
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typedef enum {
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I2C_MODE_MASTER = 0,
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I2C_MODE_SLAVE
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} i2c_mode_e;
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void i2c_set_clk(uint32_t base, uint16_t clk_div);
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void i2c_set_mode(uint32_t base, i2c_mode_e mode);
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void i2c_master_set_write(uint32_t base, uint8_t yes);
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void i2c_set_interrupt_enable(uint32_t base, uint8_t en);
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void i2c_clear_irq_pending(uint32_t base);
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uint8_t i2c_get_irq_pending(uint32_t base);
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void i2c_master_set_info(uint32_t base, uint8_t addr, uint8_t reg, uint8_t data);
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uint8_t i2c_master_get_data(uint32_t base);
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void i2c_slave_set_address(uint32_t base, uint8_t addr);
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void i2c_slave_set_ready(uint32_t base, uint8_t yes);
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uint8_t i2c_slave_op_read(uint32_t base);
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uint32_t i2c_slave_get_op_address(uint32_t base);
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uint32_t i2c_slave_get_op_data(uint32_t base);
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void i2c_slave_set_rsp_data(uint32_t base, uint32_t data);
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void i2c_start(uint32_t base);
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void i2c_stop(uint32_t base);
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// I2C control register
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#define I2C_CTRL_REG_OFFSET 0x0
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#define I2C_CTRL_REG_RESVAL 0x0
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#define I2C_CTRL_START_BIT 0
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#define I2C_CTRL_INT_EN_BIT 1
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#define I2C_CTRL_INT_PENDING_BIT 2
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#define I2C_CTRL_MODE_BIT 3
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#define I2C_CTRL_WRITE_BIT 4
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#define I2C_CTRL_ERROR_BIT 5
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#define I2C_CTRL_SLAVE_WR_BIT 6
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#define I2C_CTRL_SLAVE_RDY_BIT 7
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#define I2C_CTRL_SLAVE_ADDR_MASK 0xff
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#define I2C_CTRL_SLAVE_ADDR_OFFSET 8
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#define I2C_CTRL_SLAVE_ADDR_FIELD \
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((bitfield_field32_t) { .mask = I2C_CTRL_SLAVE_ADDR_MASK, .index = I2C_CTRL_SLAVE_ADDR_OFFSET })
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#define I2C_CTRL_CLK_DIV_MASK 0xffff
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#define I2C_CTRL_CLK_DIV_OFFSET 16
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#define I2C_CTRL_CLK_DIV_FIELD \
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((bitfield_field32_t) { .mask = I2C_CTRL_CLK_DIV_MASK, .index = I2C_CTRL_CLK_DIV_OFFSET })
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// I2C master transfer data register
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#define I2C_MASTER_DATA_REG_OFFSET 0x4
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#define I2C_MASTER_DATA_REG_RESVAL 0x0
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#define I2C_MASTER_DATA_ADDRESS_MASK 0xff
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#define I2C_MASTER_DATA_ADDRESS_OFFSET 0
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#define I2C_MASTER_DATA_ADDRESS_FIELD \
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((bitfield_field32_t) { .mask = I2C_MASTER_DATA_ADDRESS_MASK, .index = I2C_MASTER_DATA_ADDRESS_OFFSET })
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#define I2C_MASTER_DATA_REGREG_MASK 0xff
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#define I2C_MASTER_DATA_REGREG_OFFSET 8
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#define I2C_MASTER_DATA_REGREG_FIELD \
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((bitfield_field32_t) { .mask = I2C_MASTER_DATA_REGREG_MASK, .index = I2C_MASTER_DATA_REGREG_OFFSET })
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#define I2C_MASTER_DATA_DATA_MASK 0xff
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#define I2C_MASTER_DATA_DATA_OFFSET 16
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#define I2C_MASTER_DATA_DATA_FIELD \
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((bitfield_field32_t) { .mask = I2C_MASTER_DATA_DATA_MASK, .index = I2C_MASTER_DATA_DATA_OFFSET })
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// I2C slave read or write address register
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#define I2C_SLAVE_ADDR_REG_OFFSET 0x8
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#define I2C_SLAVE_ADDR_REG_RESVAL 0x0
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// I2C slave write data register
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#define I2C_SLAVE_WDATA_REG_OFFSET 0xc
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#define I2C_SLAVE_WDATA_REG_RESVAL 0x0
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// I2C slave read data register
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#define I2C_SLAVE_RDATA_REG_OFFSET 0x10
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#define I2C_SLAVE_RDATA_REG_RESVAL 0x0
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif // _I2C_REG_DEFS_
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// End generated register defines for i2c
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