319 lines
9.7 KiB
Systemverilog
319 lines
9.7 KiB
Systemverilog
/*
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Copyright 2019 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.sv"
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// tinyriscv处理器核顶层模块
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module tinyriscv_core(
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input wire clk,
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input wire rst_n,
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output wire[31:0] dbus_addr_o,
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input wire[31:0] dbus_data_i,
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output wire[31:0] dbus_data_o,
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output wire[3:0] dbus_sel_o,
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output wire dbus_we_o,
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output wire dbus_req_valid_o,
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input wire dbus_req_ready_i,
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input wire dbus_rsp_valid_i,
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output wire dbus_rsp_ready_o,
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output wire[31:0] ibus_addr_o, // 取指地址
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input wire[31:0] ibus_data_i, // 取到的指令内容
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output wire[31:0] ibus_data_o,
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output wire[3:0] ibus_sel_o,
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output wire ibus_we_o,
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output wire ibus_req_valid_o,
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input wire ibus_req_ready_i,
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input wire ibus_rsp_valid_i,
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output wire ibus_rsp_ready_o,
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input wire jtag_halt_i,
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input wire[`INT_WIDTH-1:0] int_i // 中断输入信号
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);
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// ifu模块输出信号
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wire[31:0] ifetch_inst_o;
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wire[31:0] ifetch_pc_o;
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wire ifetch_inst_valid_o;
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// ifu_idu模块输出信号
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wire[31:0] if_inst_o;
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wire[31:0] if_inst_addr_o;
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wire[`INT_WIDTH-1:0] if_int_flag_o;
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// idu模块输出信号
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wire[31:0] id_inst_o;
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wire[31:0] id_inst_addr_o;
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wire[`DECINFO_WIDTH-1:0] id_dec_info_bus_o;
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wire[31:0] id_dec_imm_o;
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wire[31:0] id_dec_pc_o;
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wire[4:0] id_rs1_raddr_o;
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wire[4:0] id_rs2_raddr_o;
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wire[4:0] id_rd_waddr_o;
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wire id_rd_we_o;
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wire id_stall_o;
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wire[31:0] id_rs1_rdata_o;
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wire[31:0] id_rs2_rdata_o;
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// idu_exu模块输出信号
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wire[31:0] ie_inst_o;
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wire[31:0] ie_inst_addr_o;
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wire[`DECINFO_WIDTH-1:0] ie_dec_info_bus_o;
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wire[31:0] ie_dec_imm_o;
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wire[31:0] ie_dec_pc_o;
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wire[31:0] ie_rs1_rdata_o;
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wire[31:0] ie_rs2_rdata_o;
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wire[4:0] ie_rd_waddr_o;
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wire ie_rd_we_o;
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// exu模块输出信号
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wire[31:0] ex_mem_wdata_o;
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wire[31:0] ex_mem_addr_o;
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wire ex_mem_we_o;
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wire[3:0] ex_mem_sel_o;
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wire ex_mem_req_valid_o;
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wire ex_mem_rsp_ready_o;
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wire ex_mem_access_misaligned_o;
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wire[31:0] ex_reg_wdata_o;
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wire ex_reg_we_o;
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wire[4:0] ex_reg_waddr_o;
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wire ex_hold_flag_o;
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wire ex_jump_flag_o;
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wire[31:0] ex_jump_addr_o;
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wire[31:0] ex_csr_wdata_o;
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wire ex_csr_we_o;
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wire[31:0] ex_csr_waddr_o;
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wire[31:0] ex_csr_raddr_o;
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wire ex_inst_ecall_o;
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wire ex_inst_ebreak_o;
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wire ex_inst_mret_o;
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// gpr_reg模块输出信号
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wire[31:0] regs_rdata1_o;
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wire[31:0] regs_rdata2_o;
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// csr_reg模块输出信号
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wire[31:0] csr_ex_data_o;
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wire[31:0] csr_clint_data_o;
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wire[31:0] csr_mtvec_o;
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wire[31:0] csr_mepc_o;
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wire[31:0] csr_mstatus_o;
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// pipe_ctrl模块输出信号
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wire[31:0] ctrl_flush_addr_o;
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wire ctrl_flush_o;
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wire[`STALL_WIDTH-1:0] ctrl_stall_o;
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// clint模块输出信号
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wire clint_csr_we_o;
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wire[31:0] clint_csr_waddr_o;
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wire[31:0] clint_csr_wdata_o;
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wire clint_stall_flag_o;
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wire[31:0] clint_int_addr_o;
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wire clint_int_assert_o;
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assign dbus_addr_o = ex_mem_addr_o;
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assign dbus_data_o = ex_mem_wdata_o;
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assign dbus_we_o = ex_mem_we_o;
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assign dbus_sel_o = ex_mem_sel_o;
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assign dbus_req_valid_o = ex_mem_req_valid_o;
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assign dbus_rsp_ready_o = ex_mem_rsp_ready_o;
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ifu u_ifu(
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.clk(clk),
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.rst_n(rst_n),
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.flush_addr_i(ctrl_flush_addr_o),
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.stall_i(ctrl_stall_o),
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.flush_i(ctrl_flush_o),
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.jtag_halt_i(jtag_halt_i),
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.inst_o(ifetch_inst_o),
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.pc_o(ifetch_pc_o),
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.inst_valid_o(ifetch_inst_valid_o),
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.ibus_addr_o(ibus_addr_o),
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.ibus_data_i(ibus_data_i),
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.ibus_data_o(ibus_data_o),
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.ibus_sel_o(ibus_sel_o),
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.ibus_we_o(ibus_we_o),
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.req_valid_o(ibus_req_valid_o),
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.req_ready_i(ibus_req_ready_i),
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.rsp_valid_i(ibus_rsp_valid_i),
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.rsp_ready_o(ibus_rsp_ready_o)
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);
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pipe_ctrl u_pipe_ctrl(
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.clk(clk),
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.rst_n(rst_n),
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.stall_from_id_i(id_stall_o),
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.stall_from_ex_i(ex_hold_flag_o),
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.stall_from_jtag_i(1'b0),
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.stall_from_clint_i(clint_stall_flag_o),
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.jump_assert_i(ex_jump_flag_o),
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.jump_addr_i(ex_jump_addr_o),
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.flush_o(ctrl_flush_o),
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.stall_o(ctrl_stall_o),
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.flush_addr_o(ctrl_flush_addr_o)
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);
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gpr_reg u_gpr_reg(
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.clk(clk),
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.rst_n(rst_n),
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.we_i(ex_reg_we_o),
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.waddr_i(ex_reg_waddr_o),
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.wdata_i(ex_reg_wdata_o),
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.raddr1_i(id_rs1_raddr_o),
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.rdata1_o(regs_rdata1_o),
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.raddr2_i(id_rs2_raddr_o),
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.rdata2_o(regs_rdata2_o)
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);
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csr_reg u_csr_reg(
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.clk(clk),
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.rst_n(rst_n),
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.exu_we_i(ex_csr_we_o),
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.exu_raddr_i(ex_csr_raddr_o),
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.exu_waddr_i(ex_csr_waddr_o),
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.exu_wdata_i(ex_csr_wdata_o),
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.exu_rdata_o(csr_ex_data_o),
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.clint_we_i(clint_csr_we_o),
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.clint_waddr_i(clint_csr_waddr_o),
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.clint_wdata_i(clint_csr_wdata_o),
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.mtvec_o(csr_mtvec_o),
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.mepc_o(csr_mepc_o),
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.mstatus_o(csr_mstatus_o)
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);
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ifu_idu u_ifu_idu(
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.clk(clk),
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.rst_n(rst_n),
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.inst_i(ifetch_inst_o),
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.inst_addr_i(ifetch_pc_o),
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.stall_i(ctrl_stall_o),
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.flush_i(ctrl_flush_o),
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.inst_valid_i(ifetch_inst_valid_o),
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.inst_o(if_inst_o),
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.inst_addr_o(if_inst_addr_o)
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);
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idu u_idu(
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.clk(clk),
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.rst_n(rst_n),
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.inst_i(if_inst_o),
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.rs1_rdata_i(regs_rdata1_o),
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.rs2_rdata_i(regs_rdata2_o),
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.inst_o(id_inst_o),
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.inst_addr_i(if_inst_addr_o),
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.rs1_rdata_o(id_rs1_rdata_o),
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.rs2_rdata_o(id_rs2_rdata_o),
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.stall_o(id_stall_o),
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.dec_info_bus_o(id_dec_info_bus_o),
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.dec_imm_o(id_dec_imm_o),
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.dec_pc_o(id_dec_pc_o),
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.rs1_raddr_o(id_rs1_raddr_o),
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.rs2_raddr_o(id_rs2_raddr_o),
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.rd_waddr_o(id_rd_waddr_o),
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.rd_we_o(id_rd_we_o)
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);
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idu_exu u_idu_exu(
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.clk(clk),
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.rst_n(rst_n),
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.inst_i(id_inst_o),
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.stall_i(ctrl_stall_o),
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.flush_i(ctrl_flush_o),
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.dec_info_bus_i(id_dec_info_bus_o),
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.dec_imm_i(id_dec_imm_o),
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.dec_pc_i(id_dec_pc_o),
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.rs1_rdata_i(id_rs1_rdata_o),
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.rs2_rdata_i(id_rs2_rdata_o),
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.rd_waddr_i(id_rd_waddr_o),
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.rd_we_i(id_rd_we_o),
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.inst_o(ie_inst_o),
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.dec_info_bus_o(ie_dec_info_bus_o),
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.dec_imm_o(ie_dec_imm_o),
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.dec_pc_o(ie_dec_pc_o),
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.rs1_rdata_o(ie_rs1_rdata_o),
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.rs2_rdata_o(ie_rs2_rdata_o),
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.rd_waddr_o(ie_rd_waddr_o),
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.rd_we_o(ie_rd_we_o)
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);
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exu u_exu(
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.clk(clk),
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.rst_n(rst_n),
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.reg1_rdata_i(ie_rs1_rdata_o),
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.reg2_rdata_i(ie_rs2_rdata_o),
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.mem_rdata_i(dbus_data_i),
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.mem_req_ready_i(dbus_req_ready_i),
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.mem_rsp_valid_i(dbus_rsp_valid_i),
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.mem_wdata_o(ex_mem_wdata_o),
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.mem_addr_o(ex_mem_addr_o),
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.mem_we_o(ex_mem_we_o),
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.mem_sel_o(ex_mem_sel_o),
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.mem_req_valid_o(ex_mem_req_valid_o),
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.mem_rsp_ready_o(ex_mem_rsp_ready_o),
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.mem_access_misaligned_o(ex_mem_access_misaligned_o),
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.reg_wdata_o(ex_reg_wdata_o),
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.reg_we_o(ex_reg_we_o),
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.reg_waddr_o(ex_reg_waddr_o),
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.hold_flag_o(ex_hold_flag_o),
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.jump_flag_o(ex_jump_flag_o),
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.jump_addr_o(ex_jump_addr_o),
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.int_assert_i(clint_int_assert_o),
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.int_addr_i(clint_int_addr_o),
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.inst_ecall_o(ex_inst_ecall_o),
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.inst_ebreak_o(ex_inst_ebreak_o),
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.inst_mret_o(ex_inst_mret_o),
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.int_stall_i(clint_stall_flag_o),
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.csr_raddr_o(ex_csr_raddr_o),
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.csr_rdata_i(csr_ex_data_o),
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.csr_wdata_o(ex_csr_wdata_o),
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.csr_we_o(ex_csr_we_o),
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.csr_waddr_o(ex_csr_waddr_o),
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.dec_info_bus_i(ie_dec_info_bus_o),
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.dec_imm_i(ie_dec_imm_o),
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.dec_pc_i(ie_dec_pc_o),
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.next_pc_i(if_inst_addr_o),
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.rd_waddr_i(ie_rd_waddr_o),
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.rd_we_i(ie_rd_we_o)
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);
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clint u_clint(
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.clk(clk),
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.rst_n(rst_n),
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.int_flag_i(int_i),
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.inst_ecall_i(ex_inst_ecall_o),
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.inst_ebreak_i(ex_inst_ebreak_o),
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.inst_mret_i(ex_inst_mret_o),
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.inst_addr_i(ie_dec_pc_o),
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.jump_flag_i(ex_jump_flag_o),
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.mem_access_misaligned_i(ex_mem_access_misaligned_o),
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.csr_mtvec_i(csr_mtvec_o),
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.csr_mepc_i(csr_mepc_o),
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.csr_mstatus_i(csr_mstatus_o),
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.csr_we_o(clint_csr_we_o),
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.csr_waddr_o(clint_csr_waddr_o),
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.csr_wdata_o(clint_csr_wdata_o),
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.stall_flag_o(clint_stall_flag_o),
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.int_addr_o(clint_int_addr_o),
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.int_assert_o(clint_int_assert_o)
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);
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endmodule
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