tinyriscv/rtl/perips
liangkangnan 64041b4d2b rtl: perips: rewrite timer module
Signed-off-by: liangkangnan <liangkangnan@163.com>
2021-08-10 09:47:37 +08:00
..
timer rtl: perips: rewrite timer module 2021-08-10 09:47:37 +08:00
uart rtl: perips: rewrite uart module 2021-08-07 14:28:46 +08:00
gpio.sv add perips 2021-05-14 21:00:57 +08:00
ram.sv temp commit 2021-07-09 15:18:09 +08:00
rom.sv temp commit 2021-07-09 15:18:09 +08:00
rvic.sv rtl:perips: add rvic 2021-07-22 09:36:04 +08:00