tinyriscv/rtl
liangkangnan 92e1e5a77a sim: add dump wave enable by softwave
Signed-off-by: liangkangnan <liangkangnan@163.com>
2021-08-20 11:50:21 +08:00
..
core rtl:perips: add i2c master 2021-08-19 09:43:12 +08:00
debug temp commit 2021-05-31 10:27:01 +08:00
perips rtl:perips: add i2c master 2021-08-19 09:43:12 +08:00
sys_bus temp commit 2021-06-19 16:33:50 +08:00
top sim: add dump wave enable by softwave 2021-08-20 11:50:21 +08:00
utils rtl:perips: rewrite gpio 2021-08-13 09:33:15 +08:00