135 lines
4.7 KiB
Systemverilog
135 lines
4.7 KiB
Systemverilog
/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module i2c_core (
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input logic clk_i,
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input logic rst_ni,
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output logic scl_o,
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output logic scl_oe_o,
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input logic scl_i,
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output logic sda_o,
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output logic sda_oe_o,
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input logic sda_i,
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output logic irq_o,
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input logic reg_we_i,
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input logic reg_re_i,
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input logic [31:0] reg_wdata_i,
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input logic [ 3:0] reg_be_i,
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input logic [31:0] reg_addr_i,
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output logic [31:0] reg_rdata_o
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);
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import i2c_reg_pkg::*;
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i2c_reg_pkg::i2c_reg2hw_t reg2hw;
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i2c_reg_pkg::i2c_hw2reg_t hw2reg;
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logic master_mode;
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logic slave_mode;
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logic op_write;
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logic op_read;
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logic start;
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logic [15:0] clk_div;
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logic int_enable;
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logic [7:0] master_address;
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logic [7:0] master_register;
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logic [7:0] master_data;
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logic master_ready, master_ready_q;
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logic master_start;
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logic master_error;
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logic [7:0] master_read_data;
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assign master_mode = ~reg2hw.ctrl.mode.q;
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assign slave_mode = reg2hw.ctrl.mode.q;
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assign op_write = ~reg2hw.ctrl.write.q;
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assign op_read = reg2hw.ctrl.write.q;
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assign start = reg2hw.ctrl.start.q;
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assign clk_div = reg2hw.ctrl.clk_div.q;
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assign int_enable = reg2hw.ctrl.int_en.q;
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assign master_address = reg2hw.master_data.address.q;
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assign master_register = reg2hw.master_data.regreg.q;
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assign master_data = reg2hw.master_data.data.q;
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// 软件写1启动master传输
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assign master_start = reg2hw.ctrl.start.qe && reg2hw.ctrl.start.q && master_ready;
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// master传输完成后，硬件清start位
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assign hw2reg.ctrl.start.d = 1'b0;
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// master传输完成上升沿脉冲
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assign hw2reg.ctrl.start.de = (~master_ready_q) && master_ready;
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// 传输完成产生中断pending
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assign hw2reg.ctrl.int_pending.d = 1'b1;
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assign hw2reg.ctrl.int_pending.de = int_enable && (~master_ready_q) && master_ready;
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// 传输完成并且是读操作，则更新master data
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assign hw2reg.master_data.data.d = master_read_data;
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assign hw2reg.master_data.data.de = op_read && (~master_ready_q) && master_ready;
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// 传输完成更新error
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assign hw2reg.ctrl.error.d = master_error;
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assign hw2reg.ctrl.error.de = (~master_ready_q) && master_ready;
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assign irq_o = reg2hw.ctrl.int_pending.q;
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (~rst_ni) begin
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master_ready_q <= 1'b1;
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end else begin
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master_ready_q <= master_ready;
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end
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end
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i2c_master u_i2c_master (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.enable_i (master_mode),
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.div_ratio_i (clk_div),
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.read_i (op_read),
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.slave_addr_i (master_address),
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.slave_reg_i (master_register),
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.slave_data_i (master_data),
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.start_i (master_start),
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.ready_o (master_ready),
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.error_o (master_error),
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.data_o (master_read_data),
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.scl_i (scl_i),
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.scl_o (scl_o),
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.scl_oe_o (scl_oe_o),
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.sda_i (sda_i),
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.sda_o (sda_o),
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.sda_oe_o (sda_oe_o)
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);
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i2c_reg_top u_i2c_reg_top (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.reg2hw (reg2hw),
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.hw2reg (hw2reg),
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.reg_we (reg_we_i),
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.reg_re (reg_re_i),
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.reg_wdata (reg_wdata_i),
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.reg_be (reg_be_i),
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.reg_addr (reg_addr_i),
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.reg_rdata (reg_rdata_o)
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);
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endmodule
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