126 lines
3.9 KiB
C
126 lines
3.9 KiB
C
// Generated register defines for spi
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// Copyright information found in source file:
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// Copyright lowRISC contributors.
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// Licensing information found in source file:
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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#ifndef _SPI_REG_DEFS_
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#define _SPI_REG_DEFS_
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Register width
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#define SPI_PARAM_REG_WIDTH 32
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#define SPI0_BASE_ADDR (0x07000000)
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#define SPI0_REG(offset) (*((volatile uint32_t *)(SPI0_BASE_ADDR + offset)))
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#define SPI0_TX_FIFO_LEN (8)
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#define SPI0_RX_FIFO_LEN SPI0_TX_FIFO_LEN
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typedef enum {
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SPI_ROLE_MODE_MASTER = 0,
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SPI_ROLE_MODE_SLAVE
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} spi_role_mode_e;
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typedef enum {
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SPI_CPOL_0_CPHA_0 = 0,
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SPI_CPOL_0_CPHA_1,
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SPI_CPOL_1_CPHA_0,
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SPI_CPOL_1_CPHA_1
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} spi_cp_mode_e;
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typedef enum {
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SPI_MODE_STANDARD = 0,
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SPI_MODE_DUAL,
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SPI_MODE_QUAD
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} spi_spi_mode_e;
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void spi0_set_clk_div(uint16_t div);
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void spi0_set_role_mode(spi_role_mode_e mode);
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void spi0_set_spi_mode(spi_spi_mode_e mode);
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void spi0_set_cp_mode(spi_cp_mode_e mode);
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void spi0_set_enable(uint8_t en);
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void spi0_set_interrupt_enable(uint8_t en);
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void spi0_set_msb_first();
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void spi0_set_lsb_first();
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void spi0_set_txdata(uint8_t data);
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uint8_t spi0_get_rxdata();
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uint8_t spi0_reset_rxfifo();
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uint8_t spi0_tx_fifo_full();
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uint8_t spi0_tx_fifo_empty();
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uint8_t spi0_rx_fifo_full();
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uint8_t spi0_rx_fifo_empty();
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void spi0_set_ss_ctrl_by_sw(uint8_t yes);
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void spi0_set_ss_level(uint8_t level);
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uint8_t spi0_get_interrupt_pending();
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void spi0_clear_interrupt_pending();
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void spi0_master_set_read();
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void spi0_master_set_write();
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void spi0_master_set_ss_delay(uint8_t clk_num);
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uint8_t spi0_master_transmiting();
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void spi0_master_write_bytes(uint8_t write_data[], uint32_t count);
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void spi0_master_read_bytes(uint8_t read_data[], uint32_t count);
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// SPI control 0 register
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#define SPI_CTRL0_REG_OFFSET 0x0
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#define SPI_CTRL0_REG_RESVAL 0x0
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#define SPI_CTRL0_ENABLE_BIT 0
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#define SPI_CTRL0_INT_EN_BIT 1
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#define SPI_CTRL0_INT_PENDING_BIT 2
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#define SPI_CTRL0_ROLE_MODE_BIT 3
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#define SPI_CTRL0_CP_MODE_MASK 0x3
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#define SPI_CTRL0_CP_MODE_OFFSET 4
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#define SPI_CTRL0_CP_MODE_FIELD \
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((bitfield_field32_t) { .mask = SPI_CTRL0_CP_MODE_MASK, .index = SPI_CTRL0_CP_MODE_OFFSET })
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#define SPI_CTRL0_SPI_MODE_MASK 0x3
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#define SPI_CTRL0_SPI_MODE_OFFSET 6
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#define SPI_CTRL0_SPI_MODE_FIELD \
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((bitfield_field32_t) { .mask = SPI_CTRL0_SPI_MODE_MASK, .index = SPI_CTRL0_SPI_MODE_OFFSET })
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#define SPI_CTRL0_READ_BIT 8
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#define SPI_CTRL0_MSB_FIRST_BIT 9
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#define SPI_CTRL0_SS_SW_CTRL_BIT 10
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#define SPI_CTRL0_SS_LEVEL_BIT 11
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#define SPI_CTRL0_SS_DELAY_MASK 0xf
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#define SPI_CTRL0_SS_DELAY_OFFSET 12
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#define SPI_CTRL0_SS_DELAY_FIELD \
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((bitfield_field32_t) { .mask = SPI_CTRL0_SS_DELAY_MASK, .index = SPI_CTRL0_SS_DELAY_OFFSET })
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#define SPI_CTRL0_CLK_DIV_MASK 0x7
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#define SPI_CTRL0_CLK_DIV_OFFSET 29
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#define SPI_CTRL0_CLK_DIV_FIELD \
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((bitfield_field32_t) { .mask = SPI_CTRL0_CLK_DIV_MASK, .index = SPI_CTRL0_CLK_DIV_OFFSET })
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// SPI status register
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#define SPI_STATUS_REG_OFFSET 0x4
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#define SPI_STATUS_REG_RESVAL 0x0
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#define SPI_STATUS_TX_FIFO_FULL_BIT 0
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#define SPI_STATUS_TX_FIFO_EMPTY_BIT 1
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#define SPI_STATUS_RX_FIFO_FULL_BIT 2
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#define SPI_STATUS_RX_FIFO_EMPTY_BIT 3
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#define SPI_STATUS_BUSY_BIT 4
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// SPI TX data register
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#define SPI_TXDATA_REG_OFFSET 0x8
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#define SPI_TXDATA_REG_RESVAL 0x0
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#define SPI_TXDATA_TXDATA_MASK 0xff
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#define SPI_TXDATA_TXDATA_OFFSET 0
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#define SPI_TXDATA_TXDATA_FIELD \
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((bitfield_field32_t) { .mask = SPI_TXDATA_TXDATA_MASK, .index = SPI_TXDATA_TXDATA_OFFSET })
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// SPI RX data register
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#define SPI_RXDATA_REG_OFFSET 0xc
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#define SPI_RXDATA_REG_RESVAL 0x0
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#define SPI_RXDATA_RXDATA_MASK 0xff
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#define SPI_RXDATA_RXDATA_OFFSET 0
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#define SPI_RXDATA_RXDATA_FIELD \
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((bitfield_field32_t) { .mask = SPI_RXDATA_RXDATA_MASK, .index = SPI_RXDATA_RXDATA_OFFSET })
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif // _SPI_REG_DEFS_
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// End generated register defines for spi
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