78 lines
2.6 KiB
Verilog
78 lines
2.6 KiB
Verilog
`timescale 1 ns / 1 ps
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`include "defines.v"
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// top module
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module openriscv_core_tb;
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reg clk;
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reg rst;
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always #10 clk = ~clk; // 50MHz
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wire[`RegBus] x3 = u_openriscv_core.u_regs.regs[3];
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wire[`RegBus] x26 = u_openriscv_core.u_regs.regs[26];
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wire[`RegBus] x27 = u_openriscv_core.u_regs.regs[27];
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integer r;
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initial begin
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clk = 0;
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rst = `RstEnable;
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$display("test running...");
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#40
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rst = `RstDisable;
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#100
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wait(x26 == 32'b1) // wait sim end, when x26 == 1
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#100
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if (x27 == 32'b1) begin
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$display("~~~~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~");
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$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
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$display("~~~~~~~~~ ##### ## #### #### ~~~~~~~~~");
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$display("~~~~~~~~~ # # # # # # ~~~~~~~~~");
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$display("~~~~~~~~~ # # # # #### #### ~~~~~~~~~");
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$display("~~~~~~~~~ ##### ###### # #~~~~~~~~~");
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$display("~~~~~~~~~ # # # # # # #~~~~~~~~~");
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$display("~~~~~~~~~ # # # #### #### ~~~~~~~~~");
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$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
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end else begin
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$display("~~~~~~~~~~~~~~~~~~~ TEST_FAIL ~~~~~~~~~~~~~~~~~~~~");
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$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
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$display("~~~~~~~~~~###### ## # # ~~~~~~~~~~");
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$display("~~~~~~~~~~# # # # # ~~~~~~~~~~");
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$display("~~~~~~~~~~##### # # # # ~~~~~~~~~~");
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$display("~~~~~~~~~~# ###### # # ~~~~~~~~~~");
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$display("~~~~~~~~~~# # # # # ~~~~~~~~~~");
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$display("~~~~~~~~~~# # # # ######~~~~~~~~~~");
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$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
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$display("fail testnum = %2d", x3);
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for (r = 0; r < 32; r++)
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$display("x%2d = 0x%x", r, u_openriscv_core.u_regs.regs[r]);
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end
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$finish;
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end
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// sim timeout
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initial begin
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#100000
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$display("Time Out.");
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$finish;
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end
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// read mem data
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initial begin
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$readmemh ("inst.data", u_openriscv_core.u_sim_ram.ram);
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end
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// generate wave file, use by gtkwave
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initial begin
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$dumpfile("openriscv_core_tb.vcd");
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$dumpvars(0, openriscv_core_tb);
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end
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openriscv_core u_openriscv_core(
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.clk(clk),
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.rst(rst)
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);
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endmodule
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