49 lines
1.9 KiB
Systemverilog
49 lines
1.9 KiB
Systemverilog
/*
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Copyright 2019 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.sv"
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// 将指令向译码模块传递
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module ifu_idu(
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input wire clk,
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input wire rst_n,
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input wire[31:0] inst_i, // 指令内容
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input wire[31:0] inst_addr_i, // 指令地址
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input wire[`STALL_WIDTH-1:0] stall_i, // 流水线暂停
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input wire flush_i, // 流水线冲刷
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input wire inst_valid_i,
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output wire[31:0] inst_o, // 指令内容
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output wire[31:0] inst_addr_o // 指令地址
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);
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wire en = !stall_i[`STALL_ID] | flush_i;
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wire[31:0] i_inst = (flush_i)? `INST_NOP: inst_i;
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wire[31:0] inst;
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gen_en_dff #(32) inst_ff(clk, rst_n, en, i_inst, inst);
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assign inst_o = inst;
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wire[31:0] i_inst_addr = flush_i? 32'h0: inst_addr_i;
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wire[31:0] inst_addr;
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gen_en_dff #(32) inst_addr_ff(clk, rst_n, en, i_inst_addr, inst_addr);
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assign inst_addr_o = inst_addr;
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endmodule
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