66 lines
1.8 KiB
Systemverilog
66 lines
1.8 KiB
Systemverilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "../core/defines.sv"
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module rom #(
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parameter DP = 4096)(
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input wire clk,
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input wire rst_n,
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input wire[31:0] addr_i,
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input wire[31:0] data_i,
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input wire[3:0] sel_i,
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input wire we_i,
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output wire[31:0] data_o,
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input wire req_valid_i,
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output wire req_ready_o,
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output wire rsp_valid_o,
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input wire rsp_ready_i
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);
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wire[31:0] addr = addr_i[31:2];
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gen_ram #(
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.DP(DP),
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.DW(32),
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.MW(4),
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.AW(32)
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) u_gen_ram(
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.clk(clk),
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.addr_i(addr),
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.data_i(data_i),
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.sel_i(sel_i),
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.we_i(we_i),
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.data_o(data_o)
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);
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vld_rdy #(
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.CUT_READY(0)
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) u_vld_rdy(
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.clk(clk),
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.rst_n(rst_n),
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.vld_i(req_valid_i),
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.rdy_o(req_ready_o),
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.rdy_i(rsp_ready_i),
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.vld_o(rsp_valid_o)
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);
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endmodule
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