110 lines
2.6 KiB
ArmAsm
110 lines
2.6 KiB
ArmAsm
#define REGBYTES 4
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#define STORE sw
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#define LOAD lw
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.section .text.entry
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.align 2
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.global trap_entry
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trap_entry:
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addi sp, sp, -32*REGBYTES
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STORE x1, 1*REGBYTES(sp)
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STORE x2, 2*REGBYTES(sp)
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STORE x3, 3*REGBYTES(sp)
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STORE x4, 4*REGBYTES(sp)
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STORE x5, 5*REGBYTES(sp)
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STORE x6, 6*REGBYTES(sp)
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STORE x7, 7*REGBYTES(sp)
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STORE x8, 8*REGBYTES(sp)
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STORE x9, 9*REGBYTES(sp)
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STORE x10, 10*REGBYTES(sp)
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STORE x11, 11*REGBYTES(sp)
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STORE x12, 12*REGBYTES(sp)
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STORE x13, 13*REGBYTES(sp)
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STORE x14, 14*REGBYTES(sp)
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STORE x15, 15*REGBYTES(sp)
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STORE x16, 16*REGBYTES(sp)
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STORE x17, 17*REGBYTES(sp)
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STORE x18, 18*REGBYTES(sp)
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STORE x19, 19*REGBYTES(sp)
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STORE x20, 20*REGBYTES(sp)
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STORE x21, 21*REGBYTES(sp)
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STORE x22, 22*REGBYTES(sp)
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STORE x23, 23*REGBYTES(sp)
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STORE x24, 24*REGBYTES(sp)
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STORE x25, 25*REGBYTES(sp)
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#ifndef SIMULATION
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STORE x26, 26*REGBYTES(sp)
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STORE x27, 27*REGBYTES(sp)
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#endif
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STORE x28, 28*REGBYTES(sp)
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STORE x29, 29*REGBYTES(sp)
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STORE x30, 30*REGBYTES(sp)
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STORE x31, 31*REGBYTES(sp)
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csrr a0, mcause
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csrr a1, mepc
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test_if_asynchronous:
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srli a2, a0, 31 /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */
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beq a2, x0, handle_synchronous /* Branch past interrupt handing if not asynchronous. */
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call interrupt_handler
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j asynchronous_return
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handle_synchronous:
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call exception_handler
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addi a1, a1, 4
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csrw mepc, a1
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asynchronous_return:
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LOAD x1, 1*REGBYTES(sp)
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LOAD x2, 2*REGBYTES(sp)
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LOAD x3, 3*REGBYTES(sp)
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LOAD x4, 4*REGBYTES(sp)
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LOAD x5, 5*REGBYTES(sp)
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LOAD x6, 6*REGBYTES(sp)
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LOAD x7, 7*REGBYTES(sp)
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LOAD x8, 8*REGBYTES(sp)
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LOAD x9, 9*REGBYTES(sp)
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LOAD x10, 10*REGBYTES(sp)
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LOAD x11, 11*REGBYTES(sp)
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LOAD x12, 12*REGBYTES(sp)
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LOAD x13, 13*REGBYTES(sp)
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LOAD x14, 14*REGBYTES(sp)
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LOAD x15, 15*REGBYTES(sp)
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LOAD x16, 16*REGBYTES(sp)
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LOAD x17, 17*REGBYTES(sp)
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LOAD x18, 18*REGBYTES(sp)
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LOAD x19, 19*REGBYTES(sp)
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LOAD x20, 20*REGBYTES(sp)
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LOAD x21, 21*REGBYTES(sp)
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LOAD x22, 22*REGBYTES(sp)
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LOAD x23, 23*REGBYTES(sp)
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LOAD x24, 24*REGBYTES(sp)
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LOAD x25, 25*REGBYTES(sp)
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#ifndef SIMULATION
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LOAD x26, 26*REGBYTES(sp)
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LOAD x27, 27*REGBYTES(sp)
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#endif
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LOAD x28, 28*REGBYTES(sp)
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LOAD x29, 29*REGBYTES(sp)
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LOAD x30, 30*REGBYTES(sp)
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LOAD x31, 31*REGBYTES(sp)
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addi sp, sp, 32*REGBYTES
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mret
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.weak interrupt_handler
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interrupt_handler:
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1:
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j 1b
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.weak exception_handler
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exception_handler:
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2:
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j 2b
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