768 lines
17 KiB
Systemverilog
768 lines
17 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Register Top module auto-generated by `reggen`
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module i2c_reg_top (
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input logic clk_i,
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input logic rst_ni,
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// To HW
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output i2c_reg_pkg::i2c_reg2hw_t reg2hw, // Write
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input i2c_reg_pkg::i2c_hw2reg_t hw2reg, // Read
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input logic reg_we,
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input logic reg_re,
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input logic [31:0] reg_wdata,
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input logic [ 3:0] reg_be,
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input logic [31:0] reg_addr,
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output logic [31:0] reg_rdata
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);
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import i2c_reg_pkg::* ;
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localparam int AW = 5;
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localparam int DW = 32;
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localparam int DBW = DW/8; // Byte Width
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logic reg_error;
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logic addrmiss, wr_err;
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logic [DW-1:0] reg_rdata_next;
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assign reg_rdata = reg_rdata_next;
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assign reg_error = wr_err;
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// Define SW related signals
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// Format: <reg>_<field>_{wd|we|qs}
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// or <reg>_{wd|we|qs} if field == 1 or 0
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logic ctrl_we;
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logic ctrl_start_qs;
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logic ctrl_start_wd;
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logic ctrl_int_en_qs;
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logic ctrl_int_en_wd;
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logic ctrl_int_pending_qs;
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logic ctrl_int_pending_wd;
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logic ctrl_mode_qs;
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logic ctrl_mode_wd;
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logic ctrl_write_qs;
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logic ctrl_write_wd;
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logic ctrl_error_qs;
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logic ctrl_slave_wr_qs;
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logic ctrl_slave_rdy_qs;
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logic ctrl_slave_rdy_wd;
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logic [7:0] ctrl_slave_addr_qs;
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logic [7:0] ctrl_slave_addr_wd;
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logic [15:0] ctrl_clk_div_qs;
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logic [15:0] ctrl_clk_div_wd;
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logic master_data_we;
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logic [7:0] master_data_address_qs;
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logic [7:0] master_data_address_wd;
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logic [7:0] master_data_regreg_qs;
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logic [7:0] master_data_regreg_wd;
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logic [7:0] master_data_data_qs;
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logic [7:0] master_data_data_wd;
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logic [7:0] slave_addr_addr0_qs;
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logic [7:0] slave_addr_addr1_qs;
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logic [7:0] slave_addr_addr2_qs;
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logic [7:0] slave_addr_addr3_qs;
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logic [7:0] slave_wdata_wdata0_qs;
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logic [7:0] slave_wdata_wdata1_qs;
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logic [7:0] slave_wdata_wdata2_qs;
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logic [7:0] slave_wdata_wdata3_qs;
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logic slave_rdata_we;
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logic [31:0] slave_rdata_qs;
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logic [31:0] slave_rdata_wd;
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// Register instances
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// R[ctrl]: V(False)
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// F[start]: 0:0
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prim_subreg #(
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.DW (1),
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.SWACCESS("RW"),
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.RESVAL (1'h0)
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) u_ctrl_start (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_start_wd),
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// from internal hardware
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.de (hw2reg.ctrl.start.de),
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.d (hw2reg.ctrl.start.d),
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// to internal hardware
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.qe (reg2hw.ctrl.start.qe),
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.q (reg2hw.ctrl.start.q),
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// to register interface (read)
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.qs (ctrl_start_qs)
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);
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// F[int_en]: 1:1
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prim_subreg #(
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.DW (1),
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.SWACCESS("RW"),
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.RESVAL (1'h0)
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) u_ctrl_int_en (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_int_en_wd),
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// from internal hardware
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.de (hw2reg.ctrl.int_en.de),
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.d (hw2reg.ctrl.int_en.d),
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// to internal hardware
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.qe (reg2hw.ctrl.int_en.qe),
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.q (reg2hw.ctrl.int_en.q),
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// to register interface (read)
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.qs (ctrl_int_en_qs)
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);
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// F[int_pending]: 2:2
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prim_subreg #(
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.DW (1),
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.SWACCESS("W1C"),
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.RESVAL (1'h0)
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) u_ctrl_int_pending (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_int_pending_wd),
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// from internal hardware
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.de (hw2reg.ctrl.int_pending.de),
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.d (hw2reg.ctrl.int_pending.d),
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// to internal hardware
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.qe (reg2hw.ctrl.int_pending.qe),
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.q (reg2hw.ctrl.int_pending.q),
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// to register interface (read)
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.qs (ctrl_int_pending_qs)
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);
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// F[mode]: 3:3
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prim_subreg #(
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.DW (1),
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.SWACCESS("RW"),
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.RESVAL (1'h0)
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) u_ctrl_mode (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_mode_wd),
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// from internal hardware
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.de (hw2reg.ctrl.mode.de),
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.d (hw2reg.ctrl.mode.d),
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// to internal hardware
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.qe (reg2hw.ctrl.mode.qe),
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.q (reg2hw.ctrl.mode.q),
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// to register interface (read)
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.qs (ctrl_mode_qs)
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);
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// F[write]: 4:4
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prim_subreg #(
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.DW (1),
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.SWACCESS("RW"),
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.RESVAL (1'h0)
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) u_ctrl_write (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_write_wd),
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// from internal hardware
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.de (hw2reg.ctrl.write.de),
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.d (hw2reg.ctrl.write.d),
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// to internal hardware
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.qe (reg2hw.ctrl.write.qe),
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.q (reg2hw.ctrl.write.q),
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// to register interface (read)
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.qs (ctrl_write_qs)
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);
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// F[error]: 5:5
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prim_subreg #(
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.DW (1),
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.SWACCESS("RO"),
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.RESVAL (1'h0)
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) u_ctrl_error (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (1'b0),
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.wd ('0),
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// from internal hardware
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.de (hw2reg.ctrl.error.de),
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.d (hw2reg.ctrl.error.d),
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// to internal hardware
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.qe (reg2hw.ctrl.error.qe),
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.q (reg2hw.ctrl.error.q),
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// to register interface (read)
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.qs (ctrl_error_qs)
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);
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// F[slave_wr]: 6:6
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prim_subreg #(
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.DW (1),
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.SWACCESS("RO"),
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.RESVAL (1'h0)
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) u_ctrl_slave_wr (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (1'b0),
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.wd ('0),
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// from internal hardware
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.de (hw2reg.ctrl.slave_wr.de),
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.d (hw2reg.ctrl.slave_wr.d),
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// to internal hardware
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.qe (reg2hw.ctrl.slave_wr.qe),
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.q (reg2hw.ctrl.slave_wr.q),
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// to register interface (read)
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.qs (ctrl_slave_wr_qs)
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);
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// F[slave_rdy]: 7:7
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prim_subreg #(
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.DW (1),
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.SWACCESS("RW"),
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.RESVAL (1'h0)
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) u_ctrl_slave_rdy (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_slave_rdy_wd),
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// from internal hardware
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.de (hw2reg.ctrl.slave_rdy.de),
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.d (hw2reg.ctrl.slave_rdy.d),
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// to internal hardware
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.qe (reg2hw.ctrl.slave_rdy.qe),
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.q (reg2hw.ctrl.slave_rdy.q),
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// to register interface (read)
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.qs (ctrl_slave_rdy_qs)
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);
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// F[slave_addr]: 15:8
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prim_subreg #(
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.DW (8),
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.SWACCESS("RW"),
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.RESVAL (8'h0)
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) u_ctrl_slave_addr (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_slave_addr_wd),
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// from internal hardware
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.de (hw2reg.ctrl.slave_addr.de),
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.d (hw2reg.ctrl.slave_addr.d),
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// to internal hardware
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.qe (reg2hw.ctrl.slave_addr.qe),
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.q (reg2hw.ctrl.slave_addr.q),
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// to register interface (read)
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.qs (ctrl_slave_addr_qs)
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);
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// F[clk_div]: 31:16
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prim_subreg #(
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.DW (16),
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.SWACCESS("RW"),
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.RESVAL (16'h0)
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) u_ctrl_clk_div (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_clk_div_wd),
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// from internal hardware
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.de (hw2reg.ctrl.clk_div.de),
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.d (hw2reg.ctrl.clk_div.d),
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// to internal hardware
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.qe (reg2hw.ctrl.clk_div.qe),
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.q (reg2hw.ctrl.clk_div.q),
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// to register interface (read)
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.qs (ctrl_clk_div_qs)
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);
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// R[master_data]: V(False)
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// F[address]: 7:0
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prim_subreg #(
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.DW (8),
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.SWACCESS("RW"),
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.RESVAL (8'h0)
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) u_master_data_address (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (master_data_we),
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.wd (master_data_address_wd),
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// from internal hardware
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.de (hw2reg.master_data.address.de),
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.d (hw2reg.master_data.address.d),
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// to internal hardware
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.qe (),
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.q (reg2hw.master_data.address.q),
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// to register interface (read)
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.qs (master_data_address_qs)
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);
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// F[regreg]: 15:8
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prim_subreg #(
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.DW (8),
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.SWACCESS("RW"),
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.RESVAL (8'h0)
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) u_master_data_regreg (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (master_data_we),
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.wd (master_data_regreg_wd),
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// from internal hardware
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.de (hw2reg.master_data.regreg.de),
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.d (hw2reg.master_data.regreg.d),
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// to internal hardware
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.qe (),
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.q (reg2hw.master_data.regreg.q),
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// to register interface (read)
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.qs (master_data_regreg_qs)
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);
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// F[data]: 23:16
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prim_subreg #(
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.DW (8),
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.SWACCESS("RW"),
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.RESVAL (8'h0)
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) u_master_data_data (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (master_data_we),
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.wd (master_data_data_wd),
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// from internal hardware
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.de (hw2reg.master_data.data.de),
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.d (hw2reg.master_data.data.d),
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// to internal hardware
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.qe (),
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.q (reg2hw.master_data.data.q),
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// to register interface (read)
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.qs (master_data_data_qs)
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);
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// R[slave_addr]: V(False)
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// F[addr0]: 7:0
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prim_subreg #(
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.DW (8),
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.SWACCESS("RO"),
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.RESVAL (8'h0)
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) u_slave_addr_addr0 (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (1'b0),
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.wd ('0),
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// from internal hardware
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.de (hw2reg.slave_addr.addr0.de),
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.d (hw2reg.slave_addr.addr0.d),
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// to internal hardware
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.qe (),
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.q (reg2hw.slave_addr.addr0.q),
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// to register interface (read)
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.qs (slave_addr_addr0_qs)
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);
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// F[addr1]: 15:8
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prim_subreg #(
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.DW (8),
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.SWACCESS("RO"),
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.RESVAL (8'h0)
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) u_slave_addr_addr1 (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (1'b0),
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.wd ('0),
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// from internal hardware
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.de (hw2reg.slave_addr.addr1.de),
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.d (hw2reg.slave_addr.addr1.d),
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// to internal hardware
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.qe (),
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.q (reg2hw.slave_addr.addr1.q),
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// to register interface (read)
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.qs (slave_addr_addr1_qs)
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);
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// F[addr2]: 23:16
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prim_subreg #(
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.DW (8),
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.SWACCESS("RO"),
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.RESVAL (8'h0)
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) u_slave_addr_addr2 (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (1'b0),
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.wd ('0),
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// from internal hardware
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.de (hw2reg.slave_addr.addr2.de),
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.d (hw2reg.slave_addr.addr2.d),
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// to internal hardware
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.qe (),
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.q (reg2hw.slave_addr.addr2.q),
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// to register interface (read)
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.qs (slave_addr_addr2_qs)
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);
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// F[addr3]: 31:24
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prim_subreg #(
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.DW (8),
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.SWACCESS("RO"),
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.RESVAL (8'h0)
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) u_slave_addr_addr3 (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (1'b0),
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.wd ('0),
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// from internal hardware
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.de (hw2reg.slave_addr.addr3.de),
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.d (hw2reg.slave_addr.addr3.d),
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// to internal hardware
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.qe (),
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.q (reg2hw.slave_addr.addr3.q),
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// to register interface (read)
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.qs (slave_addr_addr3_qs)
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);
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// R[slave_wdata]: V(False)
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// F[wdata0]: 7:0
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prim_subreg #(
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.DW (8),
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.SWACCESS("RO"),
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.RESVAL (8'h0)
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) u_slave_wdata_wdata0 (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (1'b0),
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.wd ('0),
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// from internal hardware
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.de (hw2reg.slave_wdata.wdata0.de),
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.d (hw2reg.slave_wdata.wdata0.d),
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// to internal hardware
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.qe (),
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.q (reg2hw.slave_wdata.wdata0.q),
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// to register interface (read)
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.qs (slave_wdata_wdata0_qs)
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);
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// F[wdata1]: 15:8
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prim_subreg #(
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.DW (8),
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.SWACCESS("RO"),
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.RESVAL (8'h0)
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) u_slave_wdata_wdata1 (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (1'b0),
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.wd ('0),
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// from internal hardware
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.de (hw2reg.slave_wdata.wdata1.de),
|
|
.d (hw2reg.slave_wdata.wdata1.d),
|
|
|
|
// to internal hardware
|
|
.qe (),
|
|
.q (reg2hw.slave_wdata.wdata1.q),
|
|
|
|
// to register interface (read)
|
|
.qs (slave_wdata_wdata1_qs)
|
|
);
|
|
|
|
|
|
// F[wdata2]: 23:16
|
|
prim_subreg #(
|
|
.DW (8),
|
|
.SWACCESS("RO"),
|
|
.RESVAL (8'h0)
|
|
) u_slave_wdata_wdata2 (
|
|
.clk_i (clk_i),
|
|
.rst_ni (rst_ni),
|
|
|
|
// from register interface
|
|
.we (1'b0),
|
|
.wd ('0),
|
|
|
|
// from internal hardware
|
|
.de (hw2reg.slave_wdata.wdata2.de),
|
|
.d (hw2reg.slave_wdata.wdata2.d),
|
|
|
|
// to internal hardware
|
|
.qe (),
|
|
.q (reg2hw.slave_wdata.wdata2.q),
|
|
|
|
// to register interface (read)
|
|
.qs (slave_wdata_wdata2_qs)
|
|
);
|
|
|
|
|
|
// F[wdata3]: 31:24
|
|
prim_subreg #(
|
|
.DW (8),
|
|
.SWACCESS("RO"),
|
|
.RESVAL (8'h0)
|
|
) u_slave_wdata_wdata3 (
|
|
.clk_i (clk_i),
|
|
.rst_ni (rst_ni),
|
|
|
|
// from register interface
|
|
.we (1'b0),
|
|
.wd ('0),
|
|
|
|
// from internal hardware
|
|
.de (hw2reg.slave_wdata.wdata3.de),
|
|
.d (hw2reg.slave_wdata.wdata3.d),
|
|
|
|
// to internal hardware
|
|
.qe (),
|
|
.q (reg2hw.slave_wdata.wdata3.q),
|
|
|
|
// to register interface (read)
|
|
.qs (slave_wdata_wdata3_qs)
|
|
);
|
|
|
|
|
|
// R[slave_rdata]: V(False)
|
|
|
|
prim_subreg #(
|
|
.DW (32),
|
|
.SWACCESS("RW"),
|
|
.RESVAL (32'h0)
|
|
) u_slave_rdata (
|
|
.clk_i (clk_i),
|
|
.rst_ni (rst_ni),
|
|
|
|
// from register interface
|
|
.we (slave_rdata_we),
|
|
.wd (slave_rdata_wd),
|
|
|
|
// from internal hardware
|
|
.de (1'b0),
|
|
.d ('0),
|
|
|
|
// to internal hardware
|
|
.qe (),
|
|
.q (reg2hw.slave_rdata.q),
|
|
|
|
// to register interface (read)
|
|
.qs (slave_rdata_qs)
|
|
);
|
|
|
|
|
|
logic [4:0] addr_hit;
|
|
always_comb begin
|
|
addr_hit = '0;
|
|
addr_hit[0] = (reg_addr == I2C_CTRL_OFFSET);
|
|
addr_hit[1] = (reg_addr == I2C_MASTER_DATA_OFFSET);
|
|
addr_hit[2] = (reg_addr == I2C_SLAVE_ADDR_OFFSET);
|
|
addr_hit[3] = (reg_addr == I2C_SLAVE_WDATA_OFFSET);
|
|
addr_hit[4] = (reg_addr == I2C_SLAVE_RDATA_OFFSET);
|
|
end
|
|
|
|
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
|
|
|
|
// Check sub-word write is permitted
|
|
always_comb begin
|
|
wr_err = (reg_we &
|
|
((addr_hit[0] & (|(I2C_PERMIT[0] & ~reg_be))) |
|
|
(addr_hit[1] & (|(I2C_PERMIT[1] & ~reg_be))) |
|
|
(addr_hit[2] & (|(I2C_PERMIT[2] & ~reg_be))) |
|
|
(addr_hit[3] & (|(I2C_PERMIT[3] & ~reg_be))) |
|
|
(addr_hit[4] & (|(I2C_PERMIT[4] & ~reg_be)))));
|
|
end
|
|
|
|
assign ctrl_we = addr_hit[0] & reg_we & !reg_error;
|
|
|
|
assign ctrl_start_wd = reg_wdata[0];
|
|
|
|
assign ctrl_int_en_wd = reg_wdata[1];
|
|
|
|
assign ctrl_int_pending_wd = reg_wdata[2];
|
|
|
|
assign ctrl_mode_wd = reg_wdata[3];
|
|
|
|
assign ctrl_write_wd = reg_wdata[4];
|
|
|
|
assign ctrl_slave_rdy_wd = reg_wdata[7];
|
|
|
|
assign ctrl_slave_addr_wd = reg_wdata[15:8];
|
|
|
|
assign ctrl_clk_div_wd = reg_wdata[31:16];
|
|
assign master_data_we = addr_hit[1] & reg_we & !reg_error;
|
|
|
|
assign master_data_address_wd = reg_wdata[7:0];
|
|
|
|
assign master_data_regreg_wd = reg_wdata[15:8];
|
|
|
|
assign master_data_data_wd = reg_wdata[23:16];
|
|
assign slave_rdata_we = addr_hit[4] & reg_we & !reg_error;
|
|
|
|
assign slave_rdata_wd = reg_wdata[31:0];
|
|
|
|
// Read data return
|
|
always_comb begin
|
|
reg_rdata_next = '0;
|
|
unique case (1'b1)
|
|
addr_hit[0]: begin
|
|
reg_rdata_next[0] = ctrl_start_qs;
|
|
reg_rdata_next[1] = ctrl_int_en_qs;
|
|
reg_rdata_next[2] = ctrl_int_pending_qs;
|
|
reg_rdata_next[3] = ctrl_mode_qs;
|
|
reg_rdata_next[4] = ctrl_write_qs;
|
|
reg_rdata_next[5] = ctrl_error_qs;
|
|
reg_rdata_next[6] = ctrl_slave_wr_qs;
|
|
reg_rdata_next[7] = ctrl_slave_rdy_qs;
|
|
reg_rdata_next[15:8] = ctrl_slave_addr_qs;
|
|
reg_rdata_next[31:16] = ctrl_clk_div_qs;
|
|
end
|
|
|
|
addr_hit[1]: begin
|
|
reg_rdata_next[7:0] = master_data_address_qs;
|
|
reg_rdata_next[15:8] = master_data_regreg_qs;
|
|
reg_rdata_next[23:16] = master_data_data_qs;
|
|
end
|
|
|
|
addr_hit[2]: begin
|
|
reg_rdata_next[7:0] = slave_addr_addr0_qs;
|
|
reg_rdata_next[15:8] = slave_addr_addr1_qs;
|
|
reg_rdata_next[23:16] = slave_addr_addr2_qs;
|
|
reg_rdata_next[31:24] = slave_addr_addr3_qs;
|
|
end
|
|
|
|
addr_hit[3]: begin
|
|
reg_rdata_next[7:0] = slave_wdata_wdata0_qs;
|
|
reg_rdata_next[15:8] = slave_wdata_wdata1_qs;
|
|
reg_rdata_next[23:16] = slave_wdata_wdata2_qs;
|
|
reg_rdata_next[31:24] = slave_wdata_wdata3_qs;
|
|
end
|
|
|
|
addr_hit[4]: begin
|
|
reg_rdata_next[31:0] = slave_rdata_qs;
|
|
end
|
|
|
|
default: begin
|
|
reg_rdata_next = '1;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
// Unused signal tieoff
|
|
|
|
// wdata / byte enable are not always fully used
|
|
// add a blanket unused statement to handle lint waivers
|
|
logic unused_wdata;
|
|
logic unused_be;
|
|
assign unused_wdata = ^reg_wdata;
|
|
assign unused_be = ^reg_be;
|
|
|
|
endmodule
|