47 lines
1.6 KiB
Markdown
47 lines
1.6 KiB
Markdown
# RISC-V Test Suites
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Tests are grouped into different functional test suites targeting the different subsets of the full RISC-V specifications. There will be ISA and privilege suites.
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For information on the test framework and other documentation on the compliance tests look at : [../doc/README.adoc](../doc/README.adoc)
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Currently there are five solid test suites checked into this repository along with a few deprecated/WIP tests.
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If you are looking to check compliance of RV32I in user mode then run the suites: RV32I, RV32ICSR and RV32IFENCEI
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To see the coverage of the suites see the riscv-test-suite coverage directory for the summary/detailed reports. These are generated by Imperas by using the github.com/google/riscv-dv UVM coverage testbench and the Mentor Questa SystemVerilog simulator.
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Test suites status:
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Pretty Solid:
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* RV32I (significant improvements (Nov2019) by Imperas)
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* 48 focused tests, using the correct style/macros, excellent coverage of most instructions
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* Coverage 97.23%
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* RV32IM (developed by Imperas)
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* 8 focused tests, using the correct style/macros, excellent coverage
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* Coverage 89.95%
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* RV32IMC (developed by Imperas)
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* 25 focused tests, using the correct style/macros
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* Coverage 59.68%
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* RV32ICSR
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* 6 focused tests
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* RV32IFENCEI
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* 1 test
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Work in progress (64-bit tests):
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* RV64I (developed by Imperas)
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* 8 focused tests, using the correct style/macros
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* RV64IM (developed by Imperas)
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* 3 focused tests, using the correct style/macros
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To be worked on:
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* RV64C
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* RV32A
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* RV64A
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* RV64F
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* RV64D
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* RV32E
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* RV32EC
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* RV32EA
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* RV32EF
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* RV32ED
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